Altera Avalon Verification IP Suite Uživatelský manuál Strana 48

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signal_read_response_complete
signal_read_response_completePrototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
voidReturns:
Signals that the read response has been received and inserted into the response
queue.
Description:
Verilog HDLLanguage support:
signal_response_complete
signal_response_completePrototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
voidReturns:
Triggers when either signal_read_response_complete or signal_write_
response_complete is triggered.
Description:
Verilog HDLLanguage support:
signal_write_response_complete
signal_write_response_completePrototype:
Verilog HDL: None
VHDL: N.A.
Arguments:
voidReturns:
Signals that the write response has been received and inserted into the response
queue.
Description:
Verilog HDLLanguage support:
Avalon-MM Master BFM
Altera Corporation
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signal_read_response_complete
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