Altera Avalon Verification IP Suite Uživatelský manuál stáhnout pdf (Strana 11)

Running the Simulation ...............................................................................................................16-5

Observing the Results ...................................................................................................................16-6

Avalon-MM Verilog HDL and VHDL Testbenches.........................................17-1

Avalon-MM Verilog HDL Testbench Description...............................................................................17-1

Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave

Pair..............................................................................................................................................17-2

Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves..........17-4

Avalon-MM VHDL Testbench Description..........................................................................................17-6

Running the Testbench for a Single Avalon-MM Master and Slave Pair..............................17-7

Running the Testbench for Two Avalon-MM Masters Slaves................................................17-9

Using the VHDL BFMs .........................................................................................................................17-10

Document Revision History .............................................................................18-1

How to Contact Altera .............................................................................................................................18-2

Typographic Conventions .......................................................................................................................18-2

Altera Corporation

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Introduction to Avalon Verification IP SuiteUser Guide

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