Altera Avalon Verification IP Suite Uživatelský manuál stáhnout pdf (Strana 204)

Avalon-ST Verilog HDL Testbench

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This testbench shows how to use Avalon-ST Source and Sink BFMs to verify an Avalon-ST component using

a Qsys-generated testbench. In this example, the Avalon-ST Single-Clock FIFO buffer is the DUT. The

testbench includes both the Avalon-ST Source and Sink BFMs to verify the DUT behavior.

The following software and file are required to run the test:

• Quartus II software, version 12.0 or higher.

• ModelSim-AE software that you installed with the Quartus II software.

The ug_avalon_verification.zip file. This design example file is available for download at

www.altera.com/literature/ug/ug_avalon_verification.zip.

This testbench is available for Verilog HDL. Refer to the link below for an example VHDL testbench.

Related Information

Avalon-MM VHDL Testbench Description on page 17-6

Verifying Avalon-ST DUT

The following figure shows the testbench to verify the Avalon-ST Single-Clock FIFO buffer using the

Avalon-ST Source and Sink BFMs. The testbench includes the following components:

• The Avalon Clock Source BFM provides the clock to the DUT.

• The Reset Source BFM provides the reset to the DUT.

• The Avalon-ST Source BFM connects to the DUT and drives transactions.

• The Avalon-ST Sink BFM monitors transactions from the Avalon-ST Single-Clock FIFO buffer.

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Altera Avalon Verification IP Suite Uživatelský manuál Strana 204