Altera Avalon Verification IP Suite Uživatelský manuál stáhnout pdf (Strana 125)

signal_response_done

signal_response_donePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the response to a driven data beat is available.Description:

Verilog HDLLanguage support:

signal_src_driving_transaction

signal_src_driving_transactionPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals when the source begins to drive a transaction to the interface.Description:

Verilog HDLLanguage support:

signal_src_not_ready

signal_src_not_readyPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the ready signal is not asserted.Description:

Verilog HDLLanguage support:

signal_src_ready

signal_src_readyPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that the ready signal is asserted.Description:

Verilog HDLLanguage support:

Altera Corporation

Avalon-ST Source BFM

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signal_response_done

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Altera Avalon Verification IP Suite Uživatelský manuál Strana 125