Altera Avalon Verification IP Suite Uživatelský manuál stáhnout pdf (Strana 202)

signal_instructions_inconsistent

signal_instructions_inconsistentPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that an instruction has changed while the previous instruction has not

completed.

Description:

Verilog HDLLanguage support:

signal_known_instruction_received

signal_known_instruction_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a change has occured on the instruction interface and there is no

unknown value.

Description:

Verilog HDLLanguage support:

signal_result_done

signal_result_donePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Signals that a result has been received by the master.Description:

Verilog HDLLanguage support:

Nios II Custom Instruction Slave BFM

Altera Corporation

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signal_instructions_inconsistent

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