Altera Avalon Verification IP Suite Uživatelský manuál stáhnout pdf (Strana 110)

signal_command_received

signal_command_receivedPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a command was detected on the Avalon port.

When this event is received, the testbench responds with a set_interface_

wait_time call. This call dynamically backpressures the driving Avalon

master.

Description:

Verilog HDLLanguage support:

signal_fatal_error

signal_fatal_errorPrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that a fatal error has occured in this module.Description:

Verilog HDLLanguage support:

signal_read_response_complete

signal_read_response_completePrototype:

Verilog HDL: None

VHDL: N.A.

Arguments:

voidReturns:

Notifies the testbench that the read response has been received and inserted

into the response queue.

Description:

Verilog HDLLanguage support:

Avalon-MM Monitor

Altera Corporation

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signal_command_received

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