Altera Phase-Locked Loop Reconfiguration IP Core Uživatelský manuál stáhnout pdf

February 2012 Altera Corporation

UG-032405-6.0 User Guide

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Phase-Locked Loop Reconfiguration

(ALTPLL_RECONFIG) Megafunction

This user guide describes the features and behavior of the ALTPLL_RECONFIG

megafunction that you can configure through the parameter editor in the Quartus

software.

f This user guide assumes that you are familiar with megafunctions and how to create

them. If you are unfamiliar with Altera megafunctions or the parameter editor, refer

to the Introduction to Megafunctions User Guide.

Phase-locked loops (PLLs) use divide counters and voltage-controlled oscillator

(VCO) phase taps to perform frequency synthesis and phase shifts. In enhanced and

fast PLLs, you can reconfigure the counter settings as well as phase shift the PLL

output clock in real time. You can also change the charge-pump and loop-filter

components, which dynamically affect the PLL bandwidth. The ALTPLL_RECONFIG

megafunction implements reconfiguration logic to facilitate dynamic real-time

reconfiguration of PLLs in Altera devices. You can use the megafunction to update the

output clock frequency, PLL bandwidth, and phase shifts in real time, without

reconfiguring the entire FPGA.

Features

The ALTPLL_RECONFIG megafunction offers the following additional features to the

ALTPLL megafunction:

■ Reconfiguration of pre-scale counter (N) parameters.

■ Reconfiguration of feedback counter (M) parameters.

■ Reconfiguration of post-scale output counter (C) parameters.

■ Reconfiguration of delay element or phase shift of each counter. For Stratix

III,

Stratix IV, Cyclone

III, Cyclone IV, HardCopy

III, HardCopy IV, and

Arria

II GX devices, use the ALTPLL megafunction to access this feature.

■ Dynamic adjustment of the charge-pump current and loop-filter components to

facilitate dynamic reconfiguration of the PLL bandwidth. This feature is available

only in Arria GX, HardCopy II, Stratix II, Stratix II GX, Stratix III, and Stratix IV

devices.

■ Reconfiguration from multiple configuration files using external read-only

memory (ROM) in user mode. This feature is available only in Stratix III, Stratix IV,

Cyclone III, Cyclone IV, and Arria II GX devices. The ALTPLL_RECONFIG

supports reconfiguration from Memory Initialization File (.mif) and Hexadecimal

File (.hex).

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Strany 1 - Features

Strany 2 - Device Family Support

Page 10 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationDesign ExampleYou can download

Strany 3 - Parameter Settings

Design Example Page 11Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation6. In the MegaWizard Plug-In Man

Strany 4 - Page 4 Parameter Settings

Page 12 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation7. Click Finish. The reconfig_p

Strany 5

Design Example Page 13Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationCompiling the ALTPLL and ALTPLL_

Strany 6 - Simulation

Page 14 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation6. Launch the ModelSim-Altera s

Strany 7 - ALTPLL_RECONFIG

Design Example Page 15Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationPulse Width VariationThis design

Strany 8

Page 16 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation6. In the MegaWizard Plug-In Ma

Strany 9 - Note to Figure 6:

Design Example Page 17Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation7. Click Finish. The reconfig_pl

Strany 10 - Design Example

Page 18 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationCompiling the ALTPLL and ALTPLL

Strany 11 - Design Example Page 11

Design Example Page 19Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationSimulating the Design ExampleTo

Strany 12 - Page 12 Design Example

Page 2 Common ApplicationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporationf For more details about th

Strany 13 - Simulating the Design Example

Page 20 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationFigure 15. Reconfiguration (6.3

Strany 14 - Page 14 Design Example

Design Example Page 21Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationFigure 17. Changing Parameters (

Strany 15 - Pulse Width Variation

Page 22 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationFigure 19. Pulse Width Changes

Strany 16 - Page 16 Design Example

Design Example Page 23Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationPLL Reconfiguration with Multipl

Strany 17 - Design Example Page 17

Page 24 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationParameter Settings(Scan/Inputs/

Strany 18 - Page 18 Design Example

Design Example Page 25Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationThe ALTPLL megafunction allows y

Strany 19

Page 26 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationCompiling the ALTPLL and ALTPLL

Strany 20 - Page 20 Design Example

Design Example Page 27Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporation2. pll_reconfig_circuit:u2—This

Strany 21 - Design Example Page 21

Page 28 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation7. rom_4:u7—This represents the

Strany 22 - Page 22 Design Example

Design Example Page 29Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationFigure 23 shows how the whole st

Strany 23 - Design Example Page 23

Parameter Settings Page 3Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationParameter SettingsAltera reco

Strany 24 - Page 24 Design Example

Page 30 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationFigure 24 shows the simulation

Strany 25 - Design Example Page 25

Design Example Page 31Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationAt 170 ns, the state machine is

Strany 26 - Page 26 Design Example

Page 32 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationWhen data from the ROM is writt

Strany 27 - Design Example Page 27

Design Example Page 33Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationAt 4910 ns, the tapout_rom_commo

Strany 28 - Page 28 Design Example

Page 34 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationAt 10,170 ns, the tapout_busy s

Strany 29

Design Example Page 35Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationFigure 29. PLL Reconfiguration f

Strany 30 - Page 30 Design Example

Page 36 Design ExamplePhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationThe next part of the simulation

Strany 31 - Design Example Page 31

Specifications Page 37Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationAt 41,390 ns, the tapout_rom_com

Strany 32 - (4700 to 5040 ns)

Page 38 SpecificationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporationparameteruse_scanclk_sync_regis

Strany 33 - Note to Figure 27:

Specifications Page 39Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporationscan_chain:string := "UNUSE

Strany 34 - Note to Figure 28:

Page 4 Parameter SettingsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationYou can open a .mif in a tex

Strany 35 - Note to Figure 30:

Page 40 SpecificationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationPorts and ParametersThis sectio

Strany 36 - (41,200 to 41,450 ns)

Specifications Page 41Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corporationread_paramNoReads the parameter

Strany 37 - Specifications

Page 42 SpecificationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporationpll_areset_inNoInput signal ind

Strany 38 - VHDL Component Declaration

Specifications Page 43Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationTable 9 lists the ALTPLL_RECONFI

Strany 39 - Specifications Page 39

Page 44 SpecificationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationTable 10 lists the ALTPLL_RECON

Strany 40 - Ports and Parameters

Specifications Page 45Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationTable 11 lists the counter_type

Strany 41 - Specifications Page 41

Page 46 SpecificationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationTable 12 lists the counter_para

Strany 42 - Page 42 Specifications

Specifications Page 47Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationTable 13 lists the counter_type

Strany 43 - Specifications Page 43

Page 48 SpecificationsPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporationcounter_param[]3-bit bus that s

Strany 44 - Page 44 Specifications

Specifications Page 49Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationTable 14 lists the counter_type

Strany 45 - Table 11 lists the

Checking Design Violations With the Design Assistant Page 5Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera Corpor

Strany 46 - Table 12 lists the

Page 50 Document Revision HistoryPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationDocument Revision Hi

Strany 47 - Specifications Page 47

Document Revision History Page 51Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) MegafunctionFebruary 2012 Altera CorporationNovember 2007 3.2 Up

Strany 48 - Notes to Table 13:

Page 6 SimulationPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera CorporationSimulationYou can perform functional

Strany 49 - Specifications Page 49

Functional Description—Implementing Multiple Reconfiguration Using an External ROM Page 7Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunct

Strany 50 - Document Revision History

Page 8 Functional Description—Implementing Multiple Reconfiguration Using an External ROMPhase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunct

Strany 51

Functional Description—Implementing Multiple Reconfiguration Using an External ROM Page 9Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunct

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