Altera Stratix V Avalon-MM Interface for PCIe Solutions Uživatelský manuál Strana 42
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Table 4-5: Reset Signals
Signal Direction Description
npor
Input Active low reset signal. In the Altera hardware example designs,
npor is the OR of pin_perst and local_rstn coming from the
software Application Layer. If you do not drive a soft reset signal
from the Application Layer, this signal must be derived from
pin_perst. You cannot disable this signal. Resets the entire IP
Core and transceiver. Asynchronous.
In systems that use the hard reset controller, this signal is edge,
not level sensitive; consequently, you cannot use a low value on
this signal to hold custom logic in reset. For more information
about the hard and soft reset controllers, refer to Reset.
nreset_status
Output
Active low reset signal. It is derived from npor or pin_perstn.
You can use this signal to reset the Application Layer.
pin_perst
Input Active low reset from the PCIe reset pin of the device. pin_perst
resets the datapath and control registers. Configuration via
Protocol (CvP) requires this signal. For more information about
CvP refer to Configuration via Protocol (CvP).
Stratix V devices can have up to 4 instances of the Hard IP for
PCI Express. Each instance has its own pin_perst signal. You
must connect the pin_perst of each Hard IP instance to the
corresponding nPERST pin of the device. These pins have the
following locations:
• NPERSTL0: bottom left Hard IP and CvP blocks
• NPERSTL1: top left Hard IP block
• NPERSTR0: bottom right Hard IP block
• NPERSTR1: top right Hard IP block
For example, if you are using the Hard IP instance in the bottom
left corner of the device, you must connect pin_perst to
NPERSL0.
For maximum use of the Stratix V device, Altera recommends
that you use the bottom left Hard IP first. This is the only
location that supports CvP over a PCIe link. If your design does
not require CvP, you may select other Hard IP blocks.
Refer to the appropriate device pinout for correct pin assignment
for more detailed information about these pins. The PCI Express
Card Electromechanical Specification 2.0 specifies this pin
requires 3.3 V. You can drive this 3.3V signal to the nPERST*
UG-01097_avmm
2014.12.15
Reset
4-9
64- or 128-Bit Avalon-MM Interface to the Application Layer
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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