Altera Arria 10 Avalon-MM Uživatelský manuál

Arria 10 Avalon-MM Interface for PCIeSolutionsUser GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-01145_avmm2015.05.

Feature Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVAutomaticallyhandle out-of-ordercompletions(transparent tot

Bits Register Description Reset Value Access[6] Mask for Corrected Internal Error reported by the ApplicationLayer.1 RWS[5] Mask for configuration err

Arria 10 Reset and Clocks72015.05.14UG-01145_avmmSubscribeSend FeedbackFigure 7-1: Reset Controller in Arria 10 DevicesExample Designaltpcied_<dev&

Reset Sequence for Hard IP for PCI Express IP Core and Application LayerFigure 7-2: Hard IP for PCI Express and Application Logic Reset SequenceYour A

Figure 7-3: RX Transceiver Reset Sequencebusy_xcvr_reconfigrx_pll_lockedrx_analogresetltssmstate[4:0]txdetectrx_loopbackpipe_phystatuspipe_rxstatus[2:

For descriptions of the available reset signals, refer to Reset Signals, Status, and Link Training Signals.ClocksThe Hard IP contains a clock domain c

As this figure indicates, the IP core includes the following clock domains:coreclkout_hipTable 7-1: Application Layer Clock Frequency for All Combinat

Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip×4 Gen3 256 125 MHz×8 Gen3 256 250 MHzpld_clkcoreclkout_hip can drive the Applicatio

Interrupts for Endpoints82015.05.14UG-01145_avmmSubscribeSend FeedbackThe PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The complete

Figure 8-1: Avalon-MM Interrupt Propagation to the PCI Express LinkInterrupt Disable(Configuration Space Command Register [10])Avalon-MM-to-PCI-Expres

Generation of Avalon-MM InterruptsThe generation of Avalon-MM interrupts requires the instantiation of the CRA slave module where theinterrupt registe

Transaction LayerPacket type (TLP)(transmit support)Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVMemory ReadLock

Figure 8-2: Block Diagram for Custom Interrupt HandlerMSMSI/MSI-X IRQMSI-X Table EntriesSQsysInterconnectSMPCIe-Avalon-MMBridgeHardIP forPCIeMSI orMSI

Error Handling92015.05.14UG-01145_avmmSubscribeSend FeedbackEach PCI Express compliant device must implement a basic level of error management and can

Physical Layer ErrorsTable 9-2: Errors Detected by the Physical LayerThe following table describes errors detected by the Physical Layer. Physical Lay

Transaction Layer ErrorsTable 9-4: Errors Detected by the Transaction LayerError Type DescriptionPoisoned TLP received Uncorrectable(non-fatal)This er

Error Type DescriptionIn all cases the TLP is deleted in the Hard IP block andnot presented to the Application Layer. If the TLP is anon-posted reques

Error Type DescriptionUnexpected completion Uncorrectable(non-fatal)This error is caused by an unexpected completiontransaction. The Hard IP block han

Error Type DescriptionMalformed TLP Uncorrectable(fatal)This error is caused by any of the following conditions:• The data payload of a received TLP e

Poisoned TLPs can also set the parity error bits in the PCI Configuration Space Status register.Table 9-5: Parity Error ConditionsStatus Bit Condition

Figure 9-2: Correctable Error Status RegisterThe default value of all the bits of this register is 0. An error status bit that is set indicates that t

IP Core Architecture102015.05.14UG-01145_avmmSubscribeSend FeedbackThe Avalon-MM Arria 10 Hard IP for PCI Express implements the complete PCI Express

Transaction LayerPacket type (TLP)(transmit support)Avalon-ST Interface Avalon-MMInterfaceAvalon-MM DMA Avalon-ST Interface with SR-IOVFetch and AddAt

Figure 10-1: Arria 10 Hard IP for PCI Express Using the Avalon-MM InterfaceClockDomainCrossing(CDC)Data LinkLayer(DLL)Transaction Layer (TL)PHYMAC Har

Top-Level InterfacesAvalon-MM InterfaceAn Avalon-MM interface connects the Application Layer and the Transaction Layer. The Avalon-MMinterface impleme

Related InformationPIPE Interface Signals on page 5-14Data Link LayerThe Data Link Layer is located between the Transaction Layer and the Physical Lay

Figure 10-2: Data Link LayerTo Transaction LayerTx Transaction LayerPacket Description & DataTransaction LayerPacket GeneratorRetry BufferTo Physi

• ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and generates the sequencenumber of transmitted packets.• Transaction Layer Packet Checker—T

Figure 10-3: Physical Layer ArchitectureScrambler8B10BEncoderLane nTX+ / TX-Scrambler8B10BEncoderLane 0TX+ / TX-Descrambler8B10BDecoderLane nRX+ / RX-

The PHYMAC block comprises four main sub-blocks:• MAC Lane—Both the RX and the TX path use this block.• On the RX side, the block decodes the Physical

The Avalon-MM bridge provides three possible Avalon-MM ports: a bursting master, an optionalbursting slave, and an optional non-bursting slave. The Av

Figure 10-4: PCI Express Avalon-MM BridgeTransaction LayerPCI ExpressTx ControllerPCI ExpressRx ControllerData Link LayerPhysical LayerPCI Express Meg

Related InformationAvalon-MM RX Master Block on page 10-20Avalon‑MM Bridge TLPsThe PCI Express to Avalon-MM bridge translates the PCI Express read, wr

Device Family SupportTable 1-5: Device Family SupportDevice Family SupportArria 10Preliminary. The IP core is verified with prelimi‐nary timing models

PCI Express-to-Avalon-MM Read CompletionsThe PCI Express Avalon-MM bridge returns read completion packets to the initiating Avalon-MMmaster in the iss

Related InformationMinimizing BAR Sizes and the PCIe Address Space on page 10-15Avalon-MM-to-PCI Express Read CompletionsThe PCI Express Avalon-MM bri

Figure 10-5: Address Translation in TX and RX Directions For EndpointsTransaction,Data Link,and PHYDMAAvalon-MM32-Bit Byte AddressAvalon-MM32-Bit Byte

Minimizing BAR Sizes and the PCIe Address SpaceFor designs that include multiple BARs, you may need to modify the base address assignmentsauto-assigne

Figure 10-6: Qsys System for PCI Express with Poor Address Space UtilizationThe following figure uses a filter to hide the Conduit interfaces that are

This design is consuming 1.25 GB of PCIe address space when only 276 MBytes are actually required. Thesolution is to edit the address map to place the

Sp[1:0], that specifies 32-bit or 64-bit PCI Express addressing for the translated address. The mostsignificant bits of the Avalon-MM address are used

Figure 10-10: Avalon-MM-to-PCI Express Address TranslationThe following figure depicts the Avalon-MM-to-PCI Express address translation process. In th

Figure 10-11: Qsys Design Including Completer Only Single Dword Endpoint for PCI ExpressQsys SystemPCI ExpressRoot ComplexPCIe Linkto HostCPUAvalon-MM

TX BlockThe TX block sends completion information to the Avalon-MM Hard IP for PCI Express which sends thisinformation to the root complex. The TX com

Figure 1-2: PCI Express Application with a Single Root Port and EndpointThe following figure shows a PCI Express link between two Arria 10 FPGAs.Alter

According to the PCI Express Base Specification, if MSI_enable=0 and the Disable Legacy Interruptbit=1 in the Configuration Space Command register (0x

Design Implementation112015.05.14UG-01145_avmmSubscribeSend FeedbackCompleting your design includes additional steps to specify analog properties, pin

entering user mode. Link training occurs after calibration. Refer to Reset Sequence for Hard IP for PCIExpress IP Core and Application Layer for a des

Throughput Optimization122015.05.14UG-01145_avmmSubscribeSend FeedbackThe PCI Express Base Specification defines a flow control mechanism to ensure ef

Figure 12-1: Flow Control Update LoopCreditsConsumedCounterCreditLimitData PacketFlowControlGatingLogic(CreditCheck)AllowIncrRxBufferData PacketCredit

counter. Essentially, this means the data sink knows the data source has less than a fullMAX_PAYLOAD worth of credits, and therefore is starving.b. Wh

Nevertheless, maintaining maximum throughput of completion data packets is important. Endpointsmust offer an infinite number of completion credits. En

Optional Features132015.05.14UG-01145_avmmSubscribeSend FeedbackConfiguration via Protocol (CvP)The Hard IP for PCI Express architecture has an option

CvP has the following advantages:• Provides a simpler software model for configuration. A smart host can use the PCIe protocol and theapplication topo

Table 13-1: ECRC Operation on RX PathECRC Forwarding ECRC Check Enable(4)ECRC Status Error TLP Forward to Application LayerNoNonone No Forwardedgood N

PCIe LinkPCIe Hard IPRPSwitchPCIeHard IPRPUser ApplicationLogicPCIe Hard IPEPPCIe LinkPCIe LinkUser ApplicationLogicAltera FPGA Hard IP for PCI Expres

Table 13-2: ECRC Generation and Forwarding on TX PathAll unspecified cases are unsupported and the behavior of the Hard IP is unknown.ECRC Forwarding

Avalon-MM Testbench and Design Example142015.05.14UG-01145_avmmSubscribeSend FeedbackThis chapter introduces the Root Port or Endpoint design example

Your Application Layer design may need to handle at least the following scenarios that are not possible tocreate with the Altera testbench and the Roo

Figure 14-1: Design Example for Endpoint DesignsAPPHard IP for PCI Express Testbench for EndpointsAvalon-MMresetAvalon-MMresetDUT<instance_name>

Arria 10 Avalon-MM Root Port TestbenchThis testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces or the serial PCIExpress

Note: The DMA design example requires setting BAR 2 or BAR 3 to a minimum of 256 bytes. To run theDMA tests using MSI, you must set the Number of MSI

The block diagram contains the following elements:• The DMA design example connects to the Avalon-MM interface of the Arria 10 Hard IP for PCIExpress.

these blocks to maximize interoperability with different variation files. The following table shows themapping.Table 14-1: BAR MapMemory BAR Mapping32

• The DMA issues an MSI when the last descriptor has completed.• The data written back to BFM is checked against the data that was read from the BFM.•

Offset in BFMShared MemoryValue DescriptionDW2 0x828 0 BFM shared memory data buffer 1 upper address valueDW3 0x82c 0x2800 BFM shared memory data buff

Debug FeaturesDebug features allow observation and control of the Hard IP for faster debugging of system-levelproblems.Related InformationDebugging on

Offset in DMAControl Register(BAR2)Value DescriptionDW3 0xc 2 Last valid descriptorAfter writing the last dword, DW3, of the descriptor header, the DM

Offset in BFMShared MemoryValue DescriptionDW2 0x928 10 BFM shared memory data buffer 1 upper address valueDW3 0x92c 0x10900 BFM shared memory data bu

Offset in DMA ControlRegisters (BAR2)Value DescriptionDW3 0x1c 2 Last descriptor writtenAfter writing the last dword of the Descriptor header (DW3), t

Figure 14-3: Root Port Design Example Root Port Variation(variation_name.v)Avalon-ST Interface(altpcietb_bfm_vc_intf)Test Driver(altpcietb_bfm_driver_

The top-level of the testbench instantiates the following key files:• altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates t

Figure 14-4: Root Port BFMBFM Shared Memory(altpcietb_bfm_shmem _common)BFM Log Interface(altpcietb_bfm_log_common)Root Port RTL Model (altpcietb_bfm_

• BFM Read/Write Request Functions(altpcietb_bfm_driver_rp.v)—These functions provide the basicBFM calls for PCI Express read and write requests. For

The ebfm_cfg_rp_ep executes the following steps to initialize the Configuration Space:1. Sets the Root Port Configuration Space to enable the Root Por

configuration is unlikely to be useful in real systems. If the procedure is unable to assign the BARs,it displays an error message and stops the simul

Offset (Bytes) Description+60 ReservedThe configuration routine does not configure any advanced PCI Express capabilities such as the AERcapability.Bes

Interface Width ALMs M20K Memory Blocks Logic Registers128 1900 25 2900Avalon-MM Interface–Completer Only64 650 8 1000128 1400 12 2400Avalon-MM–Comple

Figure 14-6: Memory Space Layout—No Limit Root Complex Shared MemoryUnusedUnusedConfiguration ScratchSpace Used byRoutines - NotWriteable by UserCal

Figure 14-7: I/O Address Space Root Complex Shared MemoryUnusedConfiguration ScratchSpace Used by BFMRoutines - NotWriteable by UserCalls or EndpointB

Verilog HDL include file altpcietb_bfm_driver_rp.v. The complete list of available procedures andfunctions is as follows:• ebfm_barwr—writes data from

Location altpcietb_bfm_rdwr.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the add

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores th

Argumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. The bar_table structure stores the address assigned toeach BAR so t

ebfm_cfgwr_imm_wait ProcedureThe ebfm_cfgwr_imm_wait procedure writes up to four bytes of data to the specified configurationregister. This procedure

Location altpcietb_bfm_driver_rp.vSyntax ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr, regb_len, imm_data)Argumentsbus_numPCI Express b

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

Location altpcietb_bfm_driver_rp.vArgumentsbus_numPCI Express bus number of the target device.dev_numPCI Express device number of the target device.fn

for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim,and Synopsys VCS and VCS-MX simulators.3. Compile you

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory. This routine populates the bar_ta

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.log2_

Constant DescriptionSHMEM_FILL_QWORD_INCSpecifies a data pattern of incrementing 64-bit qwords(0x0000000000000000, 0x0000000000000001,0x00000000000000

shmem_display Verilog HDL FunctionThe shmem_display Verilog HDL function displays a block of data from the BFM shared memory.Location altpcietb_bfm_dr

Related InformationShared Memory Constants on page 14-31shmem_chk_ok FunctionThe shmem_chk_ok function checks a block of BFM shared memory against a s

Table 14-12: Log MessagesConstant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_DEBUGSpecifies deb

Constant(MessageType)Description Mask BitNoDisplayby DefaultSimulationStops byDefaultMessagePrefixEBFM_MSG_ERROR_FATAL_TB_ERRUsed for BFM test driver

ebfm_log_stop_sim Verilog HDL FunctionThe ebfm_log_stop_sim procedure stops the simulation.Location altpcietb_bfm_driver_rp.vSyntax Verilog VHDL: retu

Related InformationBFM Log and Message Procedures on page 14-34ebfm_log_open Verilog HDL FunctionThe ebfm_log_open procedure opens a log file of the s

Location altpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 7:0.ReturnrangestringReturns a 2-digi

Getting Started with the Avalon‑MM Arria 10Hard IP for PCI Express22015.05.14UG-01145_avmmSubscribeSend FeedbackThis Qsys design example provides deta

Locationaltpcietb_bfm_driver_rp.vSyntax string:= himage(vec)ArgumentrangevecInput data type reg with a range of 63:0.ReturnrangestringReturns a 16-dig

dimage3This function creates a three-digit decimal string representation of the input argument that can beconcatenated into a larger message string an

Locationaltpcietb_bfm_driver_rp.vReturnrangestringReturns a 5-digit decimal representation of the input argumentthat is padded with leading 0s if nece

chained_dma_test ProcedureThe chained_dma_test procedure is the top-level procedure that runs the chaining DMA read and thechaining DMA writeLocation

Location altpcietb_bfm_driver_rp.vSyntaxdma_wr_test (bar_table, bar_num, use_msi, use_eplast)Argumentsbar_tableAddress of the Endpoint bar_table struc

Location altpcietb_bfm_driver_rp.vSyntaxdma_set_header (bar_table, bar_num, Descriptor_size, direction, Use_msi,Use_eplast, Bdt_msb, Bdt_lab, Msi_numb

Location altpcietb_bfm_driver_rp.vArgumentsrc_addrAddress of the BFM shared memory that is being polled.rc_dataExpected data value of the that is bein

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemory.bar_numBAR number to analyze.Bus_n

Location altpcietb_bfm_driver_rp.vArgumentsbar_tableAddress of the Endpoint bar_table structure in BFM sharedmemoryallowed_barsOne hot 6 bits BAR sele

Related InformationBFM Log and Message Procedures on page 14-34Setting Up SimulationChanging the simulation parameters reduces simulation time and pro

ContentsDatasheet... 1-1Arria 10 Avalon-MM I

• Creating a System with QsysThis document provides an introduction to Qsys.Running Qsys1. Choose Programs > Altera > Quartus II><version

Complete the following steps to disable the scrambler:1. Open <work_dir>/<variant>/testbench/<variant>_tb/simulation/submodules/altp

Debugging152015.05.14UG-01145_avmmSubscribeSend FeedbackAs you bring up your PCI Express system, you may face a number of issues related to FPGA confi

The following sections, describe how to debug the hardware bring-up flow. Altera recommends asystematic approach to diagnosing bring-up issues as illu

BIOS Enumeration IssuesBoth FPGA programming (configuration) and the initialization of a PCIe link require time. Potentially,an Altera FPGA including

Frequently Asked QuestionsA2015.05.14UG-01145_avmmSubscribeSend FeedbackThe following miscellaneous facts might be of assistance in troubleshooting:•

Lane Initialization and ReversalB2015.05.14UG-01145_avmmSubscribeSend FeedbackConnected components that include IP blocks for PCI Express need not sup

Figure B-1: Using Lane Reversal to Solve PCB Routing ProblemsThe following figure illustrates a PCI Express card with ×4 IP Root Port and a ×4 Endpoin

Additional InformationC2015.05.14UG-01145_avmmSubscribeSend FeedbackRevision History for the Avalon-MM InterfaceDate Version Changes Made2015.05.14 15

Date Version Changes Made• Removed list of static example designs from Example Designs onpage 1-9. You can derive the list from the installation direc

Date Version Changes Made• Added simulation support for Phase 2 and Phase 3 equalizationwhen requested by third-party BFM.• Added restrictions on the

Generating the Example Design1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.2. Under Testbench System, s

Date Version Changes Made• Removed discussion of pclk. This clock is not customer accessiblein Arria 10 devices.• Removed PLL from channel placement f

Typographic ConventionsThe following table shows the typographic conventions this document uses.Table C-1: Visual CueMeaningVisual Cue MeaningBold Typ

Visual Cue Meaningr An angled arrow instructs you to press the Enterkey.1., 2., 3., anda., b., c., and so on Numbered steps indicate a list of items w

The driver performs the following transactions with status of the transactions displayed in the ModelSimsimulation message window:1. Various configura

Related InformationSimulating Altera DesignsUnderstanding Simulation Log File GenerationStarting with the Quartus II 14.0 software release, simulat

a. do msim_setup.tclb. ld_debug (The debug suffix stops optimizations, improving visibility in the ModelSim waveforms.)c. run 140000 nsGenerating Quar

Adding Virtual Pin Assignment to the Quartus II Settings File (.qsf)To compile successfully you must add a virtual pin assignment statement for the PI

Related Information• Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates on page 4-5• Channel Placement and fPLL and ATX PLL Usage for t

Parameter Settings32015.05.14UG-01145_avmmSubscribeSend FeedbackArria 10 Avalon-MM System SettingsTable 3-1: System Settings for PCI ExpressParameter

Parameter Value DescriptionHighMaximum100 MHzoptimize your system. The credit allocation for the selectedsetting displays in the message pane.Refer to

Parameter Value DescriptionEnable multiplepackets per cyclefor the 256-bitinterfaceOn/Off When On, the 256-bit Avalon-ST interface supports thetransmi

Physical Layout of Hard IP In Arria 10 Devices...4-1Channel and Pin Placement for the Gen1, Gen2, and Ge

Interface System SettingsTable 3-2: Interface System SettingsParameter Value DescriptionApplication Interfacewidth64-bit128-bit256-bitSpecifies the da

Parameter Value DescriptionEnable control registeraccess (CRA) Avalon-MMslave portOn/OffAllows read and write access to bridge registers from theinter

Parameter Value DescriptionSize of address pages 4 KByte–4GByte Sets the size of the PCI Express system pages. All pagesmust be the same size. This pa

Device Identification RegistersTable 3-4: Device ID RegistersThe following table lists the default values of the read-only Device ID registers. You ca

PCI Express and PCI Capabilities ParametersThis group of parameters defines various capability properties of the IP core. Some of these parametersare

Parameter Possible Values Default Value Description• 0111 Ranges A, B, and C• 1110 Ranges B, C and D• 1111 Ranges A, B, C, and DAll other values are r

Parameter Value Default Value DescriptionTrack RXcompletionbufferoverflow onthe Avalon-ST interfaceOn/Off Off When On, the core includes the rxfx_cplb

Parameter Value DescriptionSlot clockconfigurationOn/Off When On, indicates that the Endpoint or Root Port uses thesame physical reference clock that

Parameter Value DescriptionPending BARIndicator[2:0] Specifies the function Base Address registers, locatedbeginning at 0x10 in Configuration Space, t

Parameter Value DescriptionSlot power limit0–255In combination with the Slot power scale value, specifies the upperlimit in watts on power supplied by

Enabling MSI or Legacy Interrupts ... 8-2Genera

Physical Layout of Hard IP In Arria 10 Devices42015.05.14UG-01145_avmmSubscribeSend FeedbackArria 10 devices include 1–4 hard IP blocks for PCI Expres

Figure 4-2: Arria 10 Devices with 72 Transceiver Channels and Four PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankTran

Figure 4-3: Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP BlocksTransceiverBankTransceiverBankTransceiverBankTransceiverBankTr

Channel and Pin Placement for the Gen1, Gen2, and Gen3 Data RatesThe following figures illustrate the x1, x2, x4, and x8 channel and pin placements fo

Figure 4-6: Arria 10 Gen1, Gen2, and Gen3 x4 Channel and Pin PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 3PMA Channel 2

Figure 4-8: Arria 10 Gen1 and Gen2 x1 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 2PMA Channel 0PMA Channel 3PMA Channel 2PM

Figure 4-11: Gen1 and Gen2 x8 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 3PMA Channel 2PMA Channel 1PMA Channe

Figure 4-13: Arria 10 Gen3 x2 Channel PlacementPMA Channel 5PMA Channel 4PMA Channel 3PMA Channel 0PMA Channel 4PMA Channel 3PMA Channel 2PMA Channe

64- or 128-Bit Avalon-MM Interface to theApplication Layer52015.05.14UG-01145_avmmSubscribeSend FeedbackThis chapter describes the top-level signals o

Figure 5-1: Signals in 64- or 128-Bit Avalon-MM Interface to the Application Layertx_out0[<n>-1:0]rx_in0[<n>-1:0]1-Bit Serial32-Bit Avalon

Optional Features...13-1Configuration via Protocol (CvP) ..

32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) SlaveSignalsThe optional CRA port for the full-featured IP core allows upstream PCI Expres

Table 5-2: Avalon-MM RX Master Interface SignalsSignals that include Bar number 0 also exist for BAR1–BAR5 when additional BARs are enabled.Signal Nam

Figure 5-2: Simultaneous DMA Read, DMA Write, and Target AccessRxmRead_oRxmReadDataValid_iRxmReadData_i[63:0]RxmResetRequest_oRxmAddress_o[31:0]RxmWai

Table 5-3: Avalon-MM TX Slave Interface SignalsSignal Name Direction DescriptionTxsChipSelect_iInput The system interconnect fabric asserts this signa

Signal Name Direction DescriptionTxsByteEnable_i[<w>-1:0]Input Write byte enable for data. A burst must be continuous.Therefore all intermediate

Clock SignalsTable 5-4: Clock SignalsSignal Direction DescriptionrefclkInput Reference clock for the IP core. It must have the frequencyspecified unde

Signal Direction Descriptionmust connect the pin_perst of each Hard IP instance to thecorresponding nPERST pin of the device. These pins have thefollo

Related Information• PCI Express Card Electromechanical Specification 2.0• Configuration via Protocol (CvP) Implementation in Altera FPGAs User GuideI

Signal Direction DescriptionIntxAck_oOutput This signal is the acknowledge for IntxReq_i. It is asserted for atleast one cycle either when either of t

Signal Direction Descriptionhip_reconfig_rst_nInput Active-low Avalon-MM reset. Resets all of the dynamic reconfi‐guration registers to their default

Use Third-Party PCIe Analyzer ...15-2BIOS E

Figure 5-6: Hard IP Reconfiguration Bus Timing of Read-Only Registersavmm_clkhip_reconfig_rst_nuser_modeser_shift_loadinterface_selavmm_wravmm_wrdata[

Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xlsformats.Transceiver channels are arranged i

Signal Direction Descriptiontx_deemph0Output Transmit de-emphasis selection. The Arria 10 Hard IP for PCIExpress sets the value for this signal based

Signal Direction DescriptiontxswingOutput When asserted, indicates full swing for the transmitter voltage.When deasserted indicates half swing.txsynch

Signal Direction Descriptionsim_pipe_ltssmstate0[4:0]Input andOutputLTSSM state: The LTSSM state machine encoding defines thefollowing states:• 5’b000

Signal Direction Descriptioneidleinfersel0[2:0]Output Electrical idle entry inference mechanism selection. Thefollowing encodings are defined:• 3&apos

Test SignalsTable 5-10: Test Interface SignalsThe test_in bus provides run-time control and monitoring of the internal state of the IP core.Signal Dir

Registers62015.05.14UG-01145_avmmSubscribeSend FeedbackCorrespondence between Configuration Space Registers and the PCIeSpecificationTable 6-1: Corres

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x170:0x17C Reserved N/A0x180:0x1FC Virtual channel arbit

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x018 Base Address 2Secondary Latency Timer, Subordinate

Datasheet12015.05.14UG-01145_avmmSubscribeSend FeedbackArria 10 Avalon-MM Interface for PCIe DatasheetAltera® Arria® 10 FPGAs include a configurable,

Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification0x068 MSI-X Message Control Next Cap PtrCapability IDMSI

Type 0 Configuration Space RegistersFigure 6-1: Type 0 Configuration Space Registers - Byte Address Offsets and LayoutEndpoints store configuration da

Type 1 Configuration Space RegistersFigure 6-2: Type 1 Configuration Space Registers (Root Ports)0x00000x004Device ID31242316158700x0080x00C0x0100x014

Figure 6-4: MSI-X Capability Structure0x0680x06C0x070Message Control Next Cap PtrMSI-X Table OffsetMSI-X Pending Bit Array (PBA) Offset31 24 23 16 15

Figure 6-7: PCI Express Capability Structure - Byte Address Offsets and LayoutIn the following table showing the PCI Express Capability Structure, reg

Altera-Defined VSEC RegistersFigure 6-8: VSEC RegistersThis extended capability structure supports Configuration via Protocol (CvP) programming and de

Table 6-3: Altera‑Defined Vendor Specific HeaderYou can specify these values when you instantiate the Hard IP. These registers are read-only at run-ti

Table 6-7: CvP StatusThe CvP Status register allows software to monitor the CvP status signals.Bits Register Description Reset Value Access[31:26] Res

Bits Register Description Reset Value Access[1] HIP_CLK_SEL. Selects between PMA and fabric clock when USER_MODE = 1 and PLD_CORE_READY = 1. The follo

Bits Register Description Reset Value Access[1] START_XFER. Sets the CvP output to the FPGA control blockindicating the start of a transfer.1’b0 RW[0]

Link Width in Gigabits Per Second (Gbps)x1 x2 x4 x8PCI Express Gen2(5.0 Gbps)4 8 16 32PCI Express Gen3(8.0 Gbps)7.87 15.75 31.51 63Refer to AN 456: PC

The following table describes the four subregions.Table 6-11: Avalon-MM Control and Status Register Address SpacesAddressRange Address Space Usage0x00

Address Range Register0x3070 INT-X Interrupt Enable Register for Root Ports0x3070 INT-X Interrupt Enable Register for Endpoints0x3A00-0x3A1F Avalon-MM

Bit Name Access Description[15:0] AVL_IRQ_ASSERTED[15:0] RO Current value of the Avalon-MM interrupt(IRQ) input ports to the Avalon-MM RXmaster port:•

Bits Name Access Description[15:0]AVL_IRQ_VectorRO Stores the interrupt vector of the systeminterconnect fabric. The host softwareshould read this reg

Address Name Access Description0x0904 A2P_MAILBOX1 RO Avalon-MM-to-PCI Express Mailbox 10x0908 A2P_MAILBOX2 RO Avalon-MM-to-PCI Express Mailbox 20x090

Address Bits Name Access Description0x1008[1:0]A2P_ADDR_SPACE1RW Address space indication for entry 1. This entry isavailable only if the number of tr

Bits Name Access Description[15:2] Reserved — —[16]P2A_MAILBOX_INT0RW1C 1 when the P2A_MAILBOX0 is written[17]P2A_MAILBOX_INT1RW1C 1 when the P2A_MAIL

Avalon-MM Mailbox RegistersA processor local to the interconnect fabric typically requires write access to a set of Avalon-MM-to-PCIExpress Mailbox re

Address Name AccessModeDescription0x3B14P2A_MAILBOX5RO PCI Express-to-Avalon-MM mailbox 50x3B18P2A_MAILBOX6RO PCI Express-to-Avalon-MM mailbox 60x3B1C

Byte OffsetRegister Dir Description14'h3C10 cfg_prm_cmd[15:0]O Base/Primary Command register for the PCIConfiguration Space.14'h3C14 cfg_roo

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the four Hard IP for PCI Express IP Cores.Fea

Byte OffsetRegister Dir Description14'h3C44 cfg_pr_lim_low[31:0]O The lower 32 bits of the prefetchable limit registersof the Type1 Configuration

Byte OffsetRegister Dir Description• 00101: Polling.Speed• 00110: config.Linkwidthstart• 00111: Config.Linkaccept• 01000: Config.Lanenumaccept• 01001:

Programming Model for Avalon-MM Root PortThe Application Layer writes the Root Port TLP TX Data registers with TLP formatted data for Configu‐ration R

Figure 6-11: Layout of Data with 4 Dword HeadersHeader 1 [63:32]Cycle 1Data Unaligned to QWord BoundaryData Aligned to QWord BoundaryCycle 2Header 0 [

Sending a Read TLP or Receiving a Non-Posted Completion TLPThe TLPs associated with the Non-Posted TX requests are stored in the RP_RX_CPL FIFO buffer

Table 6-25: INT‑X Interrupt Enable Register for Root Ports, 0x3070Bit Name AccessModeDescription[31:5] Reserved — —[4]RPRX_CPL_RECEIVEDRW When set to

Figure 6-12: Root Port TLP Data RegistersRX_TX_CNTLRP_RXCPL_REG0RP_RXCPL_REG1RP_RXCPL_STATUSControlRegisterAccessSlaveAvalon-MMMaster32323232646432IRQ

Root-Port Request Registers Address Range: 0x2800-0x2018Address Bits Name Access Description0x2010[31:16] Reserved — —[15:8]RP_RXCPL_STATUSR Specifies

Bits Register Description Reset Value Access[11] Mask for RX buffer posted and completion overflow error. 1b’1 RWS[10] Reserved 1b’0 RO[9] Mask for pa

Bits Register DescriptionResetValueAccess[10] Reserved.0RO[9] When set, indicates a parity error was detected on the Configu‐ration Space to TX bus in