Altera Arria 10 Avalon-MM Uživatelský manuál Strana 87
- Strana / 212
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Avalon-MM Mailbox Registers
A processor local to the interconnect fabric typically requires write access to a set of Avalon-MM-to-PCI
Express Mailbox registers and read-only access to a set of PCI Express-to-Avalon-MM Mailbox
registers. Eight mailbox registers are available.
The Avalon-MM-to-PCI Express Mailbox registers are writable at the addresses shown in the following
table. When the Avalon-MM processor writes to one of these registers the corresponding bit in the
Avalon MM to PCI Express Interrupt Status register is set to 1.
Table 6-21: Avalon-MM to PCI Express Mailbox Registers, 0x3A00–0x3A1F
Address Name Access Description
0x3A00
A2P_MAILBOX0
RW Avalon-MM-to-PCI Express mailbox 0
0x3A04
A2P_MAILBOX1
RW Avalon-MM-to-PCI Express mailbox 1
0x3A08
A2P _MAILBOX2
RW Avalon-MM-to-PCI Express mailbox 2
0x3A0C
A2P _MAILBOX3
RW Avalon-MM-to-PCI Express mailbox 3
0x3A10
A2P _MAILBOX4
RW Avalon-MM-to-PCI Express mailbox 4
0x3A14
A2P _MAILBOX5
RW Avalon-MM-to-PCI Express mailbox 5
0x3A18
A2P _MAILBOX6
RW Avalon-MM-to-PCI Express mailbox 6
0x3A1C
A2P_MAILBOX7
RW Avalon-MM-to-PCI Express mailbox 7
The PCI Express-to-Avalon-MM Mailbox registers are read-only at the addresses shown in the
following table. The Avalon-MM processor reads these registers when the corresponding bit in the PCI
Express to Avalon-MM Interrupt Status register is set to 1.
Table 6-22: PCI Express to Avalon-MM Mailbox Registers, 0x3B00–0x3B1F
Address Name Access
Mode
Description
0x3B00
P2A_MAILBOX0
RO PCI Express-to-Avalon-MM mailbox 0
0x3B04
P2A_MAILBOX1
RO PCI Express-to-Avalon-MM mailbox 1
0x3B08
P2A_MAILBOX2
RO PCI Express-to-Avalon-MM mailbox 2
0x3B0C
P2A_MAILBOX3
RO PCI Express-to-Avalon-MM mailbox 3
0x3B10
P2A_MAILBOX4
RO PCI Express-to-Avalon-MM mailbox 4
UG-01145_avmm
2015.05.14
Avalon-MM Mailbox Registers
6-21
Registers
Altera Corporation
Send Feedback
- Solutions 1
- Contents 2
- Datasheet 7
- Features 8
- Interface 9
- UG-01145_avmm 10
- 2015.05.14 10
- Release Information 12
- Device Family Support 13
- Configurations 13
- Altera FPGA 14
- Debug Features 16
- IP Core Verification 16
- Recommended Speed Grades 17
- Hard IP for PCI Express 19
- Running Qsys 20
- Generating the Example Design 21
- Time TLP Type Payload 23
- TLP Header 23
- Creating a Quartus II Project 24
- Compiling the Design 25
- Programming a Device 25
- Parameter Settings 27
- Parameter Value Description 28
- Interface System Settings 30
- Device Capabilities 34
- Error Reporting 35
- Link Capabilities 36
- MSI and MSI-X Capabilities 37
- Slot Capabilities 38
- Power Management 39
- Application Layer 48
- RX Avalon-MM Master Signals 50
- Clock Signals 55
- Signal Direction Description 56
- Serial Data Signals 60
- PIPE Interface Signals 61
- Test Signals 66
- Registers 67
- Altera-Defined VSEC Registers 75
- CvP Registers 76
- Address Range Register 80
- Bit Name Access Description 81
- Bits Name Access Description 82
- PCI Express Mailbox Registers 83
- Avalon-MM Mailbox Registers 87
- Address Name Access 88
- Description 88
- Byte Offset 88
- Register Dir Description 88
- Sending a Write TLP 93
- Bits Name Access 94
- Root Port TLP Data Registers 95
- Bits Register Description 98
- Related Information 100
- Arria 10 Reset and Clocks 101
- Clock Domains 104
- Clock Summary 106
- Interrupts for Endpoints 107
- MSI/MSI-X Support 109
- MsiIntfc_o[81:0] 110
- MsiControl_o[15:0] 110
- MsixIntfc_o[15:0] 110
- IntxReq_i 110
- IntxAck_o 110
- Error Handling 111
- Physical Layer Errors 112
- Data Link Layer Errors 112
- Transaction Layer Errors 113
- Error Type Description 114
- Status Bit Conditions 117
- Altera Corporation 118
- Send Feedback 118
- IP Core Architecture 119
- Hard IP for PCI Express 120
- Top-Level Interfaces 121
- Avalon-MM Interface 121
- Clocks and Reset 121
- Interrupts 121
- Data Link Layer 122
- Physical Layer 124
- TX Packets 125
- Avalon‑MM Bridge TLPs 129
- Byte Enable Value Description 130
- PCI Express Avalon-MM Bridge 132
- RX Block 138
- Avalon-MM RX Master Block 138
- TX Block 139
- Interrupt Handler Block 139
- Design Implementation 141
- SDC Timing Constraints 142
- Throughput Optimization 143
- Throughput of Posted Writes 145
- Optional Features 147
- ECRC on the RX Path 148
- ECRC on the TX Path 149
- TLP on Applica‐ 150
- TLP on Link Comments 150
- Subscribe 151
- Endpoint Design Example 154
- Root Complex 155
- User Application DMA 155
- Arria 10 Hard IP 155
- BAR/Address Map 156
- Avalon-MM Test Driver Module 157
- DMA Write Cycles 158
- DMA Read Cycles 160
- Offset in DMA Control 162
- Registers (BAR2) 162
- Value Description 162
- Root Port 163
- Variation 163
- (variation_name.v) 163
- Root Port BFM 164
- BFM Configuration Procedures 165
- BFM Request Interface 165
- BFM Memory Map 166
- Offset (Bytes) Description 168
- BFM Procedures and Functions 172
- Location altpcietb_bfm_rdwr.v 173
- Shared Memory Constants 181
- Constant Description 182
- Location 187
- Setting Up Simulation 199
- Debugging 201
- BIOS Enumeration Issues 203
- Frequently Asked Questions 204
- 7 6 5 4 3 2 1 0 205
- Core Config 8 4 1 205
- Additional Information 207
- Date Version Changes Made 208
- How to Contact Altera 210
- Typographic Conventions 211
- Visual Cue Meaning 212
Související produkty a manuály pro Měřící nástroje Altera Arria 10 Avalon-MM
(207 stránky)© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.065 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce