Altera Stratix V Avalon-MM Interface for PCIe Solutions Uživatelský manuál Strana 110
- Strana / 184
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
The PCI Express Base Specification requires that the refclk signal frequency be 100 MHz ±300 PPM.
The transitions between Gen1, Gen2, and Gen3 should be glitchless. pclk can be turned off for most of
the 1 ms timeout assigned for the PHY to change the clock rate; however, pclk should be stable before the
1 ms timeout expires.
Table 6-2: pclk Clock Frequency
Data Rate Frequency
Gen1 250 MHz
Gen2 500 MHz
The CDC module implements the asynchronous clock domain crossing between the PHY/MAC pclk
domain and the Data Link Layer coreclk domain. The transceiver pclk clock is connected directly to the
Hard IP for PCI Express and does not connect to the FPGA fabric.
Related Information
PCI Express Base Specification 2.1 or 3.0
coreclkout_hip
Table 6-3: Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and
Application Layer Interface Widths
The coreclkout_hip signal is derived from pclk. The following table lists frequencies for coreclkout_hip,
which are a function of the link width, data rate, and the width of the Application Layer to Transaction Layer
interface. The frequencies and widths specified in this table are maintained throughout operation. If the link
downtrains to a lesser link width or changes to a different maximum link rate, it maintains the frequencies it was
originally configured for as specified in this table. (The Hard IP throttles the interface to achieve a lower
throughput.)
Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip
×1 Gen1
64 62.5 MHz
(4)
×1 Gen1
64
125 MHz
×2 Gen1
64
125 MHz
×4 Gen1
64
125 MHz
×8 Gen1 64 250 MHz
×8 Gen1
128
125 MHz
(4)
This mode saves power
6-6
coreclkout_hip
UG-01097_avmm
2014.12.15
Altera Corporation
Reset and Clocks
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
Související produkty a manuály pro Měřící nástroje Altera Stratix V Avalon-MM Interface for PCIe Solutions
Měřící nástroje Altera OCT Uživatelský manuál
(10 stránky)
(10 stránky)
Měřící nástroje Altera Embedded Systems Development Kit, Cyclone III Edit Uživatelský manuál
(82 stránky)
(82 stránky)
Měřící nástroje Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Uživatelský manuál
(199 stránky)
(199 stránky)
Měřící nástroje Altera PHYLite Uživatelský manuál
(61 stránky)
(61 stránky)
Měřící nástroje Altera Arria GX Uživatelský manuál
(32 stránky)
(32 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.042 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce