Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Uživatelský manuál Strana 773
- Strana / 783
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
VHDL AXI3 and AXI4 Test Programs
VHDL AXI4 Slave BFM Test Program
Mentor VIP AE AXI3/4 User Guide, V10.2b
753
September 2013
push_transaction_id(read_trans, AXI4_QUEUE_ID_1, index, AXI4_PATH_3,
axi4_tr_if_3(index));
end loop;
wait;
end process;
-- handle_read : read data and response through path 4
-- This process reads data from memory and send read data/response
either at
-- burst or phase level depending upon slave working mode.
process
variable read_trans: integer;
variable burst_length : integer;
variable byte_length : integer;
variable addr : std_logic_vector(AXI4_MAX_BIT_SIZE-1 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
loop
pop_transaction_id(read_trans, AXI4_QUEUE_ID_1, index, AXI4_PATH_4,
axi4_tr_if_4(index));
set_read_data_valid_delay(read_trans, AXI4_PATH_4,
axi4_tr_if_4(index));
get_burst_length(burst_length, read_trans, index, AXI4_PATH_4,
axi4_tr_if_4(index));
for i in 0 to burst_length loop
get_read_addr(read_trans, i, 0, byte_length, addr, index,
AXI4_PATH_4, axi4_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, i, 0, byte_length, addr, data, index,
AXI4_PATH_4, axi4_tr_if_4(index));
if byte_length > 1 then
for j in 1 to byte_length-1 loop
get_read_addr(read_trans, i, j, byte_length, addr, index,
AXI4_PATH_4, axi4_tr_if_4(index));
do_byte_read(addr, data);
set_read_data(read_trans, i, j, byte_length, addr, data,
index, AXI4_PATH_4, axi4_tr_if_4(index));
end loop;
end if;
if slave_mode = AXI4_PHASE_SLAVE then
execute_read_data_phase(read_trans, i, index, AXI4_PATH_4,
axi4_tr_if_4(index));
end if;
end loop;
if slave_mode = AXI4_TRANSACTION_SLAVE then
execute_read_data_burst(read_trans, index, AXI4_PATH_4,
axi4_tr_if_4(index));
end if;
tmp_config_num_outstanding_rd_phase :=
tmp_config_num_outstanding_rd_phase - 1;
end loop;
wait;
end process;
-- handle_write_addr_ready : write address ready through path 5
-- This method assert/de-assert the write address channel ready signal.
- Verification IP Altera 1
- Edition 1
- AMBA AXI3/4 1
- User Guide 1
- Table of Contents 10
- List of Examples 13
- List of Figures 16
- List of Tables 17
- About This User Guide 19
- Protocol Restrictions 19
- Supported Simulators 20
- Simulator GCC Requirements 21
- Chapter 1 23
- Mentor VIP Altera Edition 23
- What Is a Transaction? 24
- An AXI Transaction 24
- Chapter 2 31
- SystemVerilog API Overview 31
- Transaction Record 33
- Table 2-1. Transaction Fields 35
- AXI3 BFM Delay Mode 48
- Chapter 3 51
- SystemVerilog Master API 57
- Chapter 4 87
- SystemVerilog Slave API 93
- Operational 100
- Transaction 100
- AXI3 Example 101
- AXI4 Example 101
- September 2013 107
- AXI3 BFM 109
- Helper Functions 118
- Chapter 5 121
- Monitor BFM Protocol Support 122
- Monitor Timing and Events 122
- Monitor BFM Configuration 122
- Timing Variables 124
- Slave Attributes 125
- Error Detection 125
- Monitor Assertions 126
- SystemVerilog Monitor API 127
- Prototype 128
- Arguments 128
- Arguments config_name 130
- (AXI4) Configuration name: 130
- Chapter 6 155
- SystemVerilog Tutorials 155
- AXI3 BFM Master Test Program 156
- AXI4 BFM Master Test Program 161
- Verifying a Slave DUT 162
- Verifying a Master DUT 173
- Example 6-30. process_write 184
- Example 6-31. handle_write 185
- AXI4 BFM Slave Test Program 186
- Internal Memory 187
- Example 6-44. handle_read 197
- Example 6-45. process_write 198
- Chapter 7 203
- VHDL API Overview 203
- Test Program VHDL 204
- VHDL to SV Wrapper 204
- Configuration 205
- Creating Transactions 206
- AXI4 Transaction Definition 207
- Table 7-1. Transaction Fields 209
- Transaction Field Description 209
- Protocol Transaction Fields 209
- Executing Transactions 212
- Waiting Events 213
- Access Transaction Record 214
- Operation Mode 216
- Channel Handshake Delay 217
- AXI4 BFM Handshake Delay 218
- Data Beat Done 220
- Transaction Done 220
- Chapter 8 221
- Master BFM Protocol Support 222
- Master Timing and Events 222
- Master BFM Configuration 222
- Master Assertions 225
- AXI4 Assertion Configuration 226
- VHDL Master API 227
- Protocol 233
- Arguments cache 255
- AXI4 BFM 297
- Chapter 9 365
- VHDL AXI3 and AXI4 Slave BFMs 365
- Slave BFM Configuration 366
- Slave Assertions 369
- AXI3 Assertion Configuration 370
- VHDL Slave API 371
- Returns transaction_id 378
- Chapter 10 505
- VHDL Monitor API 511
- Chapter 11 627
- VHDL Tutorials 627
- Example 11-29. handle read 656
- Example 11-38. process_write 668
- Chapter 12 673
- Running the Qsys Tool 676
- Running Simulation 679
- Example Script Processing 682
- Appendix A 685
- Assertions 685
- AXI4 Assertions 698
- Appendix B 715
- Programs 715
- Appendix C 751
- End-User License Agreement 779
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