Altera POS-PHY Level 4 IP Core Uživatelský manuál

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-IPPOSPHY4 User GuidePOS-PHY Level 4 IP CoreDocument last updated for Altera Complete Design Su

1–8 Chapter 1: About This IP CoreInstalling and Licensing IP CoresPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

6–2 Chapter 6: TestbenchReceiver Testbench DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationThe testbench consists of thr

Chapter 6: Testbench 6–3Receiver Testbench ExamplesDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThere are three pattern generati

6–4 Chapter 6: TestbenchReceiver Testbench ExamplesPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation1 To simulate errors using these

Chapter 6: Testbench 6–5Receiver Testbench ExamplesDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTable 6–4 gives examples of how

6–6 Chapter 6: TestbenchTransmitter Testbench DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTransmitter Testbench Desc

Chapter 6: Testbench 6–7Transmitter Testbench DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThe testbench consists of

6–8 Chapter 6: TestbenchTransmitter Testbench DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationWhen an error is asserted

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideA. Start-Up SequenceThis appendix applies to any SPI-4.2 transmitter and receiver p

A–2 Appendix A: Start-Up SequencePOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation1 For a 32-bit transmitter IP core, no PLLs are us

Appendix A: Start-Up Sequence A–3TroubleshootingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTroubleshootingThis section provide

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide2. Getting StartedDesign FlowFigure 2–1 shows the stages for creating a system with

A–4 Appendix A: Start-Up SequenceTroubleshootingPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation1. The PLL locked signal is not ass

Appendix A: Start-Up Sequence A–5TroubleshootingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guidedata output, and the phase relation

A–6 Appendix A: Start-Up SequenceTroubleshootingPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideB. Sharing PLLs for Multicore DesignsThis appendix explains how to share a PLL betw

B–2 Appendix B: Sharing PLLs for Multicore DesignsPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation4. Open the transmitter’s LVDS pa

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideC. Optimum Frequency for rxsys_clkThe IP core’s protocol logic and all Atlantic FIF

C–2 Appendix C: Optimum Frequency for rxsys_clkPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationIf you increase the LVDS data rate t

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideD. Board DesignPin ConstraintsThe pinouts for the Stratix® GX, and Stratix device f

D–2 Appendix D: Board DesignDesign for TestabilityPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationProbe PointsAltera recommends tha

Appendix D: Board Design D–3Design for TestabilityDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideSPI-4.2 Status Interface tstat[1:

2–2 Chapter 2: Getting StartedUsing the Parameter EditorPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation Filter IP Catalog to Show

D–4 Appendix D: Board DesignDesign for TestabilityPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideE. Programming the SPI-4.2 Calendar viathe Avalon Memory-Mapped InterfaceIntroducti

E–2 Appendix E: Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped InterfaceProgramming the SPI-4.2 CalendarPOS-PHY Level 4 IP Core User Gu

Appendix E: Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface E–3Programming the SPI-4.2 CalendarDecember 2014 Altera Corporatio

E–4 Appendix E: Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped InterfaceProgramming the SPI-4.2 CalendarPOS-PHY Level 4 IP Core User Gu

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideF. Static and Dynamic Phase AlignmentThe SPI-4.2 standard specifies two mechanisms

F–2 Appendix F: Static and Dynamic Phase AlignmentDynamic AlignmentPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationDynamic Alignmen

Appendix F: Static and Dynamic Phase Alignment F–3Altera SolutionsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideStatic AlignmentT

F–4 Appendix F: Static and Dynamic Phase AlignmentAC Timing AnalysisPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporationf For more info

Appendix F: Static and Dynamic Phase Alignment F–5AC Timing AnalysisDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1 The calculati

Chapter 2: Getting Started 2–3Upgrading Outdated IP CoresDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide Generate testbench syste

F–6 Appendix F: Static and Dynamic Phase AlignmentAC Timing AnalysisPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideG. Conversion from v2.2.xIntroductionThe POS-PHY Level 4 IP core version 2.4.x and

G–2 Appendix G: Conversion from v2.2.xReceiver SignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable G–1 shows the new v2.4.

Appendix G: Conversion from v2.2.x G–3Receiver SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guideerr_ry_msopN err_xx_msopIn ve

G–4 Appendix G: Conversion from v2.2.xTransmitter SignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTransmitter SignalsIn the

Appendix G: Conversion from v2.2.x G–5Transmitter SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTable G–2 shows the new 2.

G–6 Appendix G: Conversion from v2.2.xTransmitter SignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporationctl_ax_fth ctl_a0_txfthNo

Appendix G: Conversion from v2.2.x G–7Transmitter SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guidectl_td_mb1 ctl_tc_txmb1No

G–8 Appendix G: Conversion from v2.2.xTransmitter SignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideAdditional InformationThis chapter provides additional information about the docume

2–4 Chapter 2: Getting StartedUpgrading Outdated IP CoresPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation1 File paths in a restored

Info–2 Additional InformationTypographic ConventionsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTypographic ConventionsThe foll

Additional Information Info–3Typographic ConventionsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guidew A warning calls attention to

Info–4 Additional InformationTypographic ConventionsPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

Chapter 2: Getting Started 2–5Specify ParametersDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideSpecify ParametersTo specify the pa

2–6 Chapter 2: Getting StartedFiles Generated for Altera IP Cores (Legacy Parameter Editor)POS-PHY Level 4 IP Core User Guide December 2014 Altera Cor

Chapter 2: Getting Started 2–7Simulate the DesignDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1. After you review the generation

2–8 Chapter 2: Getting StartedSimulate the DesignPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation2. In the simulator, change the wo

Chapter 2: Getting Started 2–9Compile the Design and Program a DeviceDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide9. In the New

POS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationCopyright © 2014 Altera Corporation. All rights reserved. Altera, The Programmable

2–10 Chapter 2: Getting StartedCompile the Design and Program a DevicePOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationAfter you hav

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide3. Parameter SettingsYou customize the POS-PHY Level 4 IP core by specifying parame

3–2 Chapter 3: Parameter SettingsBasic ParametersPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable 3–1 shows the maximum LVDS d

Chapter 3: Parameter Settings 3–3Basic ParametersDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideIP Toolbench uses the LVDS data ra

3–4 Chapter 3: Parameter SettingsBasic ParametersPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationFor transmitters for individual bu

Chapter 3: Parameter Settings 3–5Basic ParametersDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideAtlantic FIFO Buffer ClockThe Atla

3–6 Chapter 3: Parameter SettingsOptional FeaturesPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationOptional FeaturesFigure 3–2 on pa

Chapter 3: Parameter Settings 3–7Optional FeaturesDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThe missing SOP and missing EOP e

3–8 Chapter 3: Parameter SettingsOptional FeaturesPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationIf you turn on Ignore backpressur

Chapter 3: Parameter Settings 3–9Optional FeaturesDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideIt is normal during the normal da

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1. About This IP CoreThe Altera® POS-PHY Level 4 MegaCore® function is an IP core t

3–10 Chapter 3: Parameter SettingsOptional FeaturesPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporationf For more information, refer to

Chapter 3: Parameter Settings 3–11Optional FeaturesDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideEach FIFO RAM block is implement

3–12 Chapter 3: Parameter SettingsProtocol ParametersPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationProtocol ParametersFigure 3–4

Chapter 3: Parameter Settings 3–13Protocol ParametersDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTo be effective, the far-end s

3–14 Chapter 3: Parameter SettingsProtocol ParametersPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationEach calendar can have indepen

Chapter 3: Parameter Settings 3–15Protocol ParametersDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideFor the Training pattern repet

3–16 Chapter 3: Parameter SettingsProtocol ParametersPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationReceiver OptionsThe Almost emp

Chapter 3: Parameter Settings 3–17Protocol ParametersDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1 FTL must be greater than zer

3–18 Chapter 3: Parameter SettingsProtocol ParametersPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide4. Functional Description—ReceiverThe POS-PHY Level 4 IP core consists of the main

1–2 Chapter 1: About This IP CoreFeaturesPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable 1–3 shows the level of support offer

4–2 Chapter 4: Functional Description—ReceiverBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationThis section describ

Chapter 4: Functional Description—Receiver 4–3Block DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideIf the DPA parameter

4–4 Chapter 4: Functional Description—ReceiverBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTo compensate for la

Chapter 4: Functional Description—Receiver 4–5Block DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide SOP8 violations. I

4–6 Chapter 4: Functional Description—ReceiverBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation Buffer status inte

Chapter 4: Functional Description—Receiver 4–7Block DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThe advantage of the

4–8 Chapter 4: Functional Description—ReceiverBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationThe port number is p

Chapter 4: Functional Description—Receiver 4–9Clock StructureDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThe FIFO buffer status

4–10 Chapter 4: Functional Description—ReceiverClock StructurePOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationIn multiple clock dom

Chapter 4: Functional Description—Receiver 4–11Clock StructureDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideIn 32-bit (quarter-ra

Chapter 1: About This IP Core 1–3General DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide Error detection and handling

4–12 Chapter 4: Functional Description—ReceiverReset StructurePOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationReset StructureBy def

Chapter 4: Functional Description—Receiver 4–13Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideSPI-4.2 P

4–14 Chapter 4: Functional Description—ReceiverError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationReserved

Chapter 4: Functional Description—Receiver 4–15Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideWhen you

4–16 Chapter 4: Functional Description—ReceiverError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationAfter the

Chapter 4: Functional Description—Receiver 4–17Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideDIP-4 Out

4–18 Chapter 4: Functional Description—ReceiverError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationThe DIP-4

Chapter 4: Functional Description—Receiver 4–19Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTable 4–4

4–20 Chapter 4: Functional Description—ReceiverError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationThe Atlan

Chapter 4: Functional Description—Receiver 4–21Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideMissing S

1–4 Chapter 1: About This IP CoreGeneral DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationInterfaces & ProtocolsThe f

4–22 Chapter 4: Functional Description—ReceiverError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationMissing E

Chapter 4: Functional Description—Receiver 4–23SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideSignalsTable 4–5 through Tabl

4–24 Chapter 4: Functional Description—ReceiverSignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable 4–7. Atlantic Receive I

Chapter 4: Functional Description—Receiver 4–25SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guideerr_ry_fifo_oflwNOutputrxsys_

4–26 Chapter 4: Functional Description—ReceiverSignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporationctl_ry_rsfrmInputrxsys_clkWhe

Chapter 4: Functional Description—Receiver 4–27SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guiderav_clkInputrav_clkAvalon-MM

4–28 Chapter 4: Functional Description—ReceiverAvalon-MM Interface Register MapPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationAval

Chapter 4: Functional Description—Receiver 4–29Avalon-MM Interface Register MapDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1 If

4–30 Chapter 4: Functional Description—ReceiverLatency InformationPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationLatency Informati

Chapter 4: Functional Description—Receiver 4–31Latency InformationDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTable 4–13 lists

Chapter 1: About This IP Core 1–5IP Core VerificationDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideIn this version of the POS-PHY

4–32 Chapter 4: Functional Description—ReceiverLatency InformationPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide5. Functional Description—TransmitterThe POS-PHY Level 4 IP core consists of the ma

5–2 Chapter 5: Functional Description—TransmitterBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationAtlantic BuffersT

Chapter 5: Functional Description—Transmitter 5–3Block DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideWhen the ignore b

5–4 Chapter 5: Functional Description—TransmitterBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationAs data is transm

Chapter 5: Functional Description—Transmitter 5–5Block DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThe training sequ

5–6 Chapter 5: Functional Description—TransmitterBlock DescriptionPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationFor 32-bit (quart

Chapter 5: Functional Description—Transmitter 5–7Block DescriptionDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideWhen the ignore b

5–8 Chapter 5: Functional Description—TransmitterClock StructurePOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationFigure 5–3 on page

Chapter 5: Functional Description—Transmitter 5–9Clock StructureDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideMultiple Clock Doma

1–6 Chapter 1: About This IP CorePerformance and Resource UtilizationPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation Table 1–4. Pe

5–10 Chapter 5: Functional Description—TransmitterClock StructurePOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationFigure 5–4 on page

Chapter 5: Functional Description—Transmitter 5–11Reset StructureDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1 The SPI-4.2 tdcl

5–12 Chapter 5: Functional Description—TransmitterError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationA DIP-

Chapter 5: Functional Description—Transmitter 5–13Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideThe st

5–14 Chapter 5: Functional Description—TransmitterError Flagging and HandlingPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable

Chapter 5: Functional Description—Transmitter 5–15Error Flagging and HandlingDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideIf a S

5–16 Chapter 5: Functional Description—TransmitterSignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationMissing EOPFigure 5–9 and

Chapter 5: Functional Description—Transmitter 5–17SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide.Table 5–3. SPI-4.2 Transm

5–18 Chapter 5: Functional Description—TransmitterSignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable 5–5. Atlantic Transm

Chapter 5: Functional Description—Transmitter 5–19SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide.Table 5–6. Atlantic Buffe

Chapter 1: About This IP Core 1–7Installing and Licensing IP CoresDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideInstalling and Li

5–20 Chapter 5: Functional Description—TransmitterSignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporationctl_ts_statedgeInput - Sta

Chapter 5: Functional Description—Transmitter 5–21SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guideerr_ts_frmOutputtsclkIndic

5–22 Chapter 5: Functional Description—TransmitterSignalsPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationTable 5–8. Data Path and C

Chapter 5: Functional Description—Transmitter 5–23SignalsDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guidectl_td_alpha[7:0]Inputtdin

5–24 Chapter 5: Functional Description—TransmitterAvalon-MM Interface Register MapPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationA

Chapter 5: Functional Description—Transmitter 5–25Avalon-MM Interface Register MapDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide1

5–26 Chapter 5: Functional Description—TransmitterLatency InformationPOS-PHY Level 4 IP Core User Guide December 2014 Altera CorporationLatency Inform

Chapter 5: Functional Description—Transmitter 5–27Latency InformationDecember 2014 Altera Corporation POS-PHY Level 4 IP Core User GuideTable 5–11 lis

5–28 Chapter 5: Functional Description—TransmitterLatency InformationPOS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation

December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide6. TestbenchThe testbench stimulates the inputs and checks the outputs of the inter