Altera SerialLite III Streaming MegaCore Function Uživatelský manuál

SerialLite III Streaming MegaCoreFunction User GuideLast updated for Altera Complete Design Suite: 15.0SubscribeSend FeedbackUG-011262015.05.04101 Inn

Getting Started32015.05.04UG-01126SubscribeSend FeedbackInstalling and Licensing IP CoresThe Altera IP Library provides many useful IP core functions

OpenCore Plus evaluation supports the following two operation modes:• Untethered—run the design containing the licensed IP for a limited time.• Tether

Arria 10 DesignsIf your design targets Arria 10 devices:• The parameter editor displays a message about the required output clock frequency of the ext

ParameterValue Default DescriptionMeta framelength200–8191 8191 Specifies the metaframe length in 8-byte words.ECCProtectionYes/No No Select to use er

ParameterValue Default DescriptionfPLLreferenceclockfrequency (1)Lane rate/64Lane rate/40See description257.812500MHzSpecifies the fPLL reference cloc

Note: If your design targets Arria 10 devices, the transceiver reconfiguration functionality is embeddedinside the transceivers. The phy_mgmt bus inte

File Name Description<system>.sopcinfo Describes the connections and IP component parameterizations inyour Qsys system. You can parse its conten

File Name Description<my_ip>.regmap If the IP contains register information, the .regmap file generates.The .regmap file describes the register

Figure 3-3: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated3. Ignore th

Figure 3-4: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

ContentsSerialLite III Streaming MegaCore Function Quick Reference...1-1About the SerialLite III Streaming IP Core...

Table 3-3: Stratix V and Arria V GZ Testbench Default Simulation ParametersParameter Default Value CommentsGenerated user clockfrequency (user_clock_f

Arria 10 Simulation TestbenchIf your design targets Arria 10 devices, the generated example testbench is dynamic and has the sameconfiguration as the

Figure 3-6: SerialLite III Streaming Example Testbench (Simplex) for Arria 10 DevicesDevice Under Test (Sink)TestbenchTrafficGeneratorTrafficCheckerSo

Table 3-4: Testbench Simulation ScriptsSimulator File DirectoryDevice FamilyScriptModelSim-Altera SE/AE<example design name>/example_testbench/v

Simulator File DirectoryDevice FamilyScriptNCSim<variation name>_sim/cadenceStratix VArria V GZncsim_setup.sh<variation name>/sim/cadence

SerialLite III Streaming IP Core FunctionalDescription42015.05.04UG-01126SubscribeSend FeedbackThe SerialLite III Streaming IP core implements a proto

Core FunctionDuplex• Data encapsulation and decapsulation• Generation and removal of Idle Control Words• User synchronization and burst marker inserti

SerialLite III Streaming Source CoreThe source core consists of five major functional blocks (the implementation varies depending on theclocking mode)

Figure 4-4: SerialLite III Streaming Source Core (Advanced Clocking Mode)ApplicationModulePHY IPCore (1)SerialLite III Streaming SourceTransceiver Rec

• For 15.625 Gbps < lane rates < 17.4 Gpbs, the fPLL outputs the user_clock/user_clock_tx based ona fixed ratio, however, the tx_coreclkin opera

SerialLite III Streaming IP Core Design Guidelines...5-1SerialLite III Streaming IP Core Design Example for Str

• Altera Transceiver PHY IP Core User GuideFor more information about the Interlaken PHY IP core and how to dynamically reconfigure the PHY.Source PPM

Figure 4-7: SerialLite III Streaming Sink Core (Advanced Clocking Mode)ApplicationModuleSerialLite III Streaming SinkTransceiver Reconfiguration Clock

• In the standard clocking mode (pure streaming), the decoding process checks the received data streamto detect idle control words that the source app

SerialLite III Streaming Duplex CoreFor Arria 10 devices, the duplex core is composed of source and sink cores interfaced with the NativePHY IP core i

tx_serial_clk input (see Signals). The Seriallite III Streaming IP core uses a transmit serial clock inputbus (tx_serial_clk) and tx_pll_locked input

Clock Domain DescriptionStandardClockingModeAdvancedClocking ModeSinkCoreuser_clockSink user interface clock (in standard clockingmode)Yesphy_mgmt_clk

Table 4-4: Comparing Standard and Advanced Clocking ModesResource Standard Mode Advanced Mode DescriptionSource userclockingCore generated User provid

Figure 4-8: SerialLite III Streaming IP Core Block Diagram in Standard Clocking ModeSerialLite IIIStreaming LinkSerialLite IIIStreaming Sink CoreLane

Note: The core operates at higher clock rates in Advanced Clocking Mode. Therefore, when operating inthis mode, it may be difficult to close timing at

Table 4-5: Latency Measurement for Duplex CoreDevice Clocking ModeParametersLatency (ns)Number of Lanes Per-Lane Data Rate(Mbps)Arria 10Standard 5 10,

SerialLite III Streaming MegaCore FunctionQuick Reference12015.05.04UG-01126SubscribeSend FeedbackThe Altera® SerialLite III Streaming MegaCore® IP fu

The 64-bit PMA interface support the higher range data rates from 15.625 to 17 Gbps:Lane Data Rate in Standard Clocking Mode = User Clock Frequency ×

CRC-32 Error InjectionIn the Quartus II software version 13.1 and higher, the SerialLite III IP core supports CRC error injectionwith the 10G PCS CRC-

Figure 4-12: Source Waveform for Continuous Mode0 8* ***ddata[127:0]sync[7:0]start_of_burstend_of_burstvalid• start_of_burst pulses for one clock cycl

Figure 4-14: Sink Waveform for Continuous Modedata[127:0]sync[7:0]start_of_burstend_of_burstvalid0 8* 18*d8• start_of_burst pulses for one clock cycle

Signal WidthClockDomainDirection Descriptiontx_pll_locked 1 N.A. Input This signal indicates that all external transceiverPLLs are locked. If more tha

Signal WidthClockDomainDirection Descriptiondata64xNuser_clockInput This vector carries the transmitted streamingdata to the core.N represents the num

Signal WidthClockDomainDirection Descriptionerror3 or 4user_clockOutput This vector indicates an overflow in the sourceadaptation module’s FIFO buffer

Signal WidthClock DomainDirection Descriptioninterface_clock1core_clockOutput Clock for data transfer across the sink coreinterface in the advanced cl

Signal WidthClock DomainDirection Descriptionend_of_burst1Standardclocking: user_clockAdvancedclocking: core_clockOutput When the core is in burst mod

Signal WidthClock DomainDirection Descriptioncore_reset1N.A.Input Asynchronous master reset for the core.Assert this signal high to reset the MAClayer

Item DescriptionIP CoreInformationCore Features • Up to 17.4 Gbps lane data rates for Arria 10 devices.• Supports 1–24 serial lanes in configurations

Signal WidthClock DomainDirection Descriptionsync_tx8Standardclocking:user_clockAdvancedclocking:core_clockInput The sync vector is an 8 bit bus. The

Signal WidthClock DomainDirection Descriptionerror_tx3 or 4Standardclocking:user_clockAdvancedclocking:core_clockOutput This vector indicates an overf

Signal WidthClock DomainDirection Descriptionlink_up_rx1Standardclocking:user_clockAdvancedclocking:core_clockOutput The core asserts this signal to i

Signal WidthClock DomainDirection Descriptionerror_rxN+5Standardclocking:user_clockAdvancedclocking:core_clockOutput This vector indicates the state o

Signal WidthClockDomainDirection Descriptionphy_mgmt_addr[N:0]9 (Stratix Vand Arria VGZ)11 - 16(Arria 10)phy_mgmt_clkInput Control and status register

Signal WidthClockDomainDirection Descriptionreconfig_to_xcvr• Sourcecore:140xN• Sinkcore:70xN• Duplexcore:140xNphy_mgmt_clkInputDynamic reconfiguratio

SerialLite III Streaming IP Core DesignGuidelines52015.05.04UG-01126SubscribeSend FeedbackSerialLite III Streaming IP Core Design Example for Stratix

Figure 5-1: Design Example for Simplex Core in Standard Clocking ModeDemoManagementAvalon MasterExport Export UARTReset ControllerTrafficGeneratorTraf

Related Information• Arria 10 Simulation Testbench on page 3-12• SerialLite III ErrataDesign Example ComponentsThe design example consists of followin

Field Bits DescriptionBurstCount58–32 Tracks the number of bursts used to transfer the sample data. This field valuestarts with one after reset and is

About the SerialLite III Streaming IP Core22015.05.04UG-01126SubscribeSend FeedbackThe SerialLite III Streaming IP core is a high-speed serial communi

loopback. If you use the design example with another device or development board, you may need toupdate the device setting and constraints.You must us

The terminal should now display an interactive session for the SerialLite III Streaming IP core designexample.Related Information• Development Kits/Ca

Source Core Link DebuggingFigure 5-4: Source Core Link Debugging Flow ChartSource LinkIink_up asserted?(Data pass throughto the transceivers?)yesnotx_

Signal Name Location Descriptiontx_sync_done/source/tx_sync_done This active high signal indicates that all thelanes are bonded by the Native PHY orIn

Sink Core Link DebuggingFigure 5-5: Sink Core Link Debugging Flow ChartSink Linkrx_alignedproperly asserted?(Indicating that thelanes are properlyalig

Signal Name Location Descriptionrx_crc32/sink/rx_crc32 This active high signal indicates CRC-32 errorfrom the CRC checker.rx_frame_lock[lanes-1:0]/sin

Condition Error Indication Core BehaviorSink CoreDiagnostic code wordCRC-32 errorThe sink core assertserror[(lanes+3)-lane]flag for one clockcycle.The

Additional Information62015.05.04UG-01126SubscribeSend FeedbackAdditional information about the document and Altera.Document Revision HistoryDate Vers

Contact(5)Contact Method AddressTechnical trainingWebsite www.altera.com/trainingEmail [email protected] literature Website www.altera.com/li

• Low protocol overhead• Low point-to-point transfer latency• Uses the hardened Native PHY IP core (Arria 10 devices) or Interlaken PHY IP core (Strat

Related Information• Standard Clocking Mode on page 4-12• Advanced Clocking Mode on page 4-13Performance and Resource UtilizationThe following table l

Device DirectionClockingModeParametersALMsLogic RegistersM20KNumberof LanesPer-LaneData Rate(Mbps)ECC Primary SecondaryStratixV GXandArriaV GZSource S