Altera POS-PHY Level 4 IP Core Uživatelský manuál Strana 122
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- Tabulka s obsahem
- ŘEŠENÍ PROBLÉMŮ
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
E–2 Appendix E: Programming the SPI-4.2 Calendar via the Avalon Memory-Mapped Interface
Programming the SPI-4.2 Calendar
POS-PHY Level 4 IP Core User Guide December 2014 Altera Corporation
1 This step is typically only required after reset or power up and prevents
accessing the calendar memories before they are configured.
2. Write a value into the
CALM0
field, to set the calendar multiplier for calendar 0.
3. Write a 5 into the
CALLEN0
field, to set the calendar length to 5 slots for calendar 0.
4. Map the calendar 0 slot numbers to the desired port numbers. The slots are
addressed indirectly via the
CALMEM_ADR
register. Write to the
CALMEM_ADR
register
first, to set the slot number, and then you can write the port number to the
CALMEM_DAT0
register.
a. Assign port 0 to slot 0:
■ Write
0
to
CALMEM_ADR
.
■ Write
0
to
CALMEM_DAT0
.
b. Assign port 3 to slot 1:
■ Write
1
to
CALMEM_ADR
.
■ Write
3
to
CALMEM_DAT0
.
c. Assign port 2 to slot 2:
■ Write
2
to
CALMEM_ADR
.
■ Write
2
to
CALMEM_DAT0
.
d. Assign port 3 to slot 3:
■ Write
3
to
CALMEM_ADR
.
■ Write
3
to
CALMEM_DAT0
.
e. Assign port 0 to slot 4:
■ Write
4
to
CALMEM_ADR
.
■ Write
0
to
CALMEM_DAT0
.
5. Write a value into the
CALM1
field, to set the calendar multiplier for calendar 1.
6. Write a 3 into the
CALLEN1
field, to set the calendar length to 3 slots for calendar 1.
7. Map the calendar 1 slot numbers to the desired port numbers:
a. Assign port 1 to slot 0:
■ Write
0
to
CALMEM_ADR
.
■ Write
1
to
CALMEM_DAT1
.
b. Assign port 2 to slot 1:
■ Write
1
to
CALMEM_ADR
.
■ Write
2
to
CALMEM_DAT1
.
c. Assign port 3 to slot 2:
■ Write
2
to
CALMEM_ADR
.
■ Write
3
to
CALMEM_DAT1
.
8. Enable the status channel by writing a 0 to the
RSFRM
bit, if required.
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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