Altera POS-PHY Level 4 IP Core Uživatelský manuál Strana 91
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- Tabulka s obsahem
- ŘEŠENÍ PROBLÉMŮ
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Chapter 5: Functional Description—Transmitter 5–21
Signals
December 2014 Altera Corporation POS-PHY Level 4 IP Core User Guide
err_ts_frm
Output
tsclk
Indicates the frame was malformed. Possible causes
are:
■ Calendar did not begin with a framing word.
■ Hitless bandwidth repositioning is turned on, and
calendar select word was not
‘b01
or
‘b10
.
■ Unexpected framing word was in the calendar
portion of the frame.
Asserted synchronous to
stat_ts_dip2state
.
err_ts_dip2
Output
Indicates the calculated DIP-2 did not match the DIP-
2 word in the status frame. Asserted synchronous to
stat_ts_dip2state
.
ctl_ts_callen[7:0]
Input
Sets the expected length of the calendar in the status
frame. This port is absent if Asymmetric Port
Support is turned on. Only change at reset, or when
ctl_ts_rsfrm
and
stat_ts_disabled
are both
asserted.
ctl_ts_calm[7:0]
Input
Sets the expected number of status calendar
repetitions between framing and DIP-2 in the status
frame. This port is absent if Asymmetric Port
Support is turned on. Only change at reset, or when
ctl_ts_rsfrm
and
stat_ts_disabled
are both
asserted.
stat_ts_calsel
Output
Indicates the currently selected calendar when
Hitless B/W reprovisioning is turned on. Zero
indicates
‘b01
, and one indicates
‘b10
. It is set to
zero when Hitless B/W reprovisioning is turned off.
This port is absent if Asymmetric Port Support is
turned off.
tav_clk
Input
tav_clk
Avalon-MM clock. Signals prefixed by
tav_
are
synchronous to this clock. This port is absent if
Asymmetric Port Support is turned off.
tav_address[3:0]
Input
Avalon-MM address. This port is absent if
Asymmetric Port Support is turned off.
tav_chipselect
Input
Avalon-MM chip select. This port is absent if
Asymmetric Port Support is turned off.
tav_write
Input
tav_clk
Avalon-MM write enable. This port is absent if
Asymmetric Port Support is turned off.
tav_read
Input
Avalon-MM read enable. This port is absent if
Asymmetric Port Support is turned off.
tav_writedata[15:0]
Input
Avalon-MM write data. This port is absent if
Asymmetric Port Support is turned off.
tav_readdata[15:0]
Output
Avalon-MM read data. This port is absent if
Asymmetric Port Support is turned off.
tav_waitrequest
Output
Avalon-MM wait request. This port is absent if
Asymmetric Port Support is turned off.
Table 5–7. SPI-4.2 Status Channel Control and Status (Part 3 of 3)
Signal Direction Clock Domain Description
- User Guide 1
- POS-PHY Level 4 IP Core 1
- 1. About This IP Core 3
- General Description 5
- Interfaces & Protocols 6
- IP Core Verification 7
- OpenCore Plus IP Evaluation 9
- 2. Getting Started 11
- Using the Parameter Editor 12
- Upgrading Outdated IP Cores 13
- Specify Parameters 15
- Simulate the Design 17
- 3. Parameter Settings 21
- LVDS Data Rate 22
- PLL Input Frequency 23
- Data Path Width 23
- Buffer Mode 23
- Basic Parameters 24
- Atlantic FIFO Buffer Clock 25
- Atlantic Interface Width 25
- Optional Features 26
- Transmitter Options 27
- Receiver Options 28
- Starving Starving Starving 29
- Starving Hungry Hungry 29
- Starving Satisfied Satisfied 29
- FIFO RAM Blocks 30
- Note to Table 3–5: 31
- Protocol Parameters 32
- Features 39
- Block Description 39
- ALTLVDS_RX IP Core 41
- Data Processor (rx_data_proc) 42
- Atlantic Buffers 43
- Individual Buffers 44
- Status Processor 45
- Notes to Figure 4–3: 46
- Note to Table 4–1: 47
- Notes to Figure 4–4: 48
- Requirements for rxsys_clk 49
- Reset Structure 50
- Error Flagging and Handling 50
- SPI-4.2 Protocol Errors 51
- Notes to Table 4–3: 53
- DIP-4 Marking 54
- Notes to Figure 4–8: 56
- Missing SOP 59
- Missing EOP 60
- Note to Table 4–7: 62
- Note to Table 4–8: 63
- Note to Table 4–9: 63
- Latency Information 68
- Data Processor (tx_data_proc) 74
- Status Bypass Port 77
- Clock Structure 78
- Multiple Clock Domain 79
- Notes to Figure 5–4: 80
- Note to Table 5–5: 88
- 6. Testbench 99
- Variation 100
- Receiver 100
- Receiver Testbench Examples 101
- 6–4 Chapter 6: Testbench 102
- Chapter 6: Testbench 6–5 103
- 6–6 Chapter 6: Testbench 104
- Chapter 6: Testbench 6–7 105
- 6–8 Chapter 6: Testbench 106
- A. Start-Up Sequence 107
- Troubleshooting 109
- Issues and Tips—Miscellaneous 111
- Separate PLLs 113
- Shared PLL 113
- "<rx_pll>" 114
- Note to Table C–1: 115
- D. Board Design 117
- Probe Points 118
- Spare Pins 119
- JTAG Scan Chain 119
- D–4 Appendix D: Board Design 120
- Design for Testability 120
- Introduction 121
- Static Alignment 125
- Dynamic Alignment 126
- Altera Solutions 126
- Dynamic Phase Alignment (DPA) 127
- AC Timing Analysis 128
- Budgets 129
- G. Conversion from v2.2.x 131
- Receiver Signals 132
- Transmitter Signals 134
- Additional Information 139
- Note to Table: 140
- Additional Information Info–3 141
- Typographic Conventions 141
- Info–4 Additional Information 142
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