Altera JESD204B IP Uživatelský manuál Strana 73
- Strana / 158
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Receiver
Table 4-6: Receiver Signals
Signal Width Direction Description
Clocks and Resets
pll_ref_clk
1 Input Transceiver reference clock signal.
rxlink_clk
1 Input RX link clock signal used by the Avalon-ST
interface. This clock is equal to RX data rate
divided by 40.
For Subclass 1, you cannot use the output of
rxphy_clk signal as rxlink_clk signal. To sample
SYSREF correctly, the core PLL must provide the
rxlink_clk signal and must be configured as
normal operating mode.
rxlink_rst_n_reset_n
1 Input Reset for the RX link clock signal. This reset is an
active low signal.
rxphy_clk[]
L Output Recovered clock signal. This clock is derived from
the clock data recovery (CDR) and the frequency
depends on the JESD204B IP core data rate.
rx_digitalreset[]
(25)
L Input Reset for the transceiver PCS block. This reset is an
active high signal.
rx_analogreset[]
(25)
L Input Reset for the CDR and transceiver PMA block.
This reset is an active high signal.
rx_islockedtodata[]
(25)
L Output This signal is asserted to indicate that the RX CDR
PLL is locked to the RX data and the RX CDR has
changed from LTR to LTD mode.
rx_cal_busy[]
(25)
L Output RX calibration in progress signal. This signal is
asserted to indicate that the RX transceiver calibra‐
tion is in progress.
Signal Width Direction Description
Transceiver Interface
rx_serial_data[]
L Input Differential high speed serial input data. The clock
is recovered from the serial data stream.
(25)
The Transceiver PHY Reset Controller IP Core controls this signal.
4-36
Receiver
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Functional Description
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Související produkty a manuály pro Měřící nástroje Altera JESD204B IP
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(3 stránky)
(3 stránky)
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(80 stránky)
(80 stránky)
Měřící nástroje Altera SCFIFO Uživatelský manuál
(28 stránky)
(28 stránky)
Měřící nástroje Altera Serial Digital Interface (SDI) MegaCore Function Uživatelský manuál
(140 stránky)
(140 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.037 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce