Altera JESD204B IP Uživatelský manuál stáhnout pdf (Strana 28)

In the .sdc file for your project, make the following command changes:

• Specify the PLL clock reference pin frequency using the create_clock command.

• Derive the PLL generated output clocks from the Altera PLL IP Core (for Arria V, Cyclone V and

Stratix V) or Altera I/O PLL IP Core (for Arria 10) using the derive_pll_clocks command.

• Comment out the create_clock commands for the txlink_clk, reconfig_to_xcvr[0] or

reconfig_clk, and tx_avs_clk, rxlink_clk, and rx_avs_clk clocks in the altera_jesd204.sdc file.

• Identify the base and generated clock name that correlates to the txlink_clk, reconfig_clk, and

tx_avs_clk, rxlink_clk, and rx_avs_clk clocks using the report_clock command.

• Describe the relationship between base and generated clocks in the design using the

set_clock_groups command.

After you complete your design, you must modify the clock names in your .sdc file to the full-design clock

names, taking into account both the IP core instance name in the full design, and the design hierarchy. Be

careful when adding the timing exceptions based on your design, for example, when the JESD204B IP

core handles asynchronous timing between the txlink_clk, rxlink_clk, pll_ref_clk, tx_avs_clk,

rx_avs_clk, and reconfig_clk (for Arria 10 only) clocks.

The table below shows an example of clock names in the altera_jesd204.sdc and input clock names in the

user design. In this example, there is a dedicated input clock for the transceiver TX PLL and CDR at the

refclk pin. The device_clk is the input to the core PLL clkin pin. The IP core and transceiver Avalon-

MM interfaces have separate external clock sources with different frequencies.

3-14

Timing Constraints For Input Clocks

UG-01142

2015.05.04

Altera Corporation

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Altera JESD204B IP Uživatelský manuál Strana 28