Altera JESD204B IP Uživatelský manuál Strana 24
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Table 3-3: Simulation Run Scripts
Simulator File Directory Script
ModelSim-Altera
SE/AE
<example_design_directory>/ip_sim/testbench/mentor run_altera_jesd204_tb.tcl
VCS <example_design_directory>/ip_sim/testbench/synopsys/vcs run_altera_jesd204_tb.sh
VCS MX <example_design_directory>/ip_sim/testbench/synopsys/
vcsmx
run_altera_jesd204_tb.sh
Aldec Riviera <example_design_directory>/ip_sim/testbench/aldec run_altera_jesd204_tb.tcl
Cadence <example_design_directory>/ip_sim/testbench/cadence run_altera_jesd204_tb.sh
To simulate the testbench design using the ModelSim-Altera or Aldec Riviera-PRO simulator, follow
these steps:
1. Launch the ModelSim-Altera or Aldec Riviera-PRO simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/
<simulator name>.
3. On the File menu, click Load > Macro file. Select run_altera_jes204_tb.tcl. This file compiles the
design and runs the simulation automatically, providing a pass/fail indication on completion.
To simulate the testbench design using the VCS, VCS MX (in Linux), or Cadence simulator, follow these
steps:
1. Launch the VCS, VCS MX, or Cadence simulator.
2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/
<simulator name>.
3. Run the run_altera_jes204_tb.sh file. This file compiles the design and runs the simulation automati‐
cally, providing a pass/fail indication on completion.
Related Information
Simulating Altera Designs
More information about Altera simulation models.
Compiling the JESD204B IP Core Design
Before you begin
Refer to the JESD204B IP Core Design Considerations on page 3-11 before compiling the JESD204B
IP core design.
To compile your design, click Start Compilation on the Processing menu in the Quartus II software. You
can use the generated .qip file to include relevant files into your project.
Related Information
• JESD204B IP Core Design Considerations on page 3-11
• Quartus II Help
More information about compilation in Quartus II software.
3-10
Compiling the JESD204B IP Core Design
UG-01142
2015.05.04
Altera Corporation
Getting Started
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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