Altera JESD204B IP Uživatelský manuál stáhnout pdf (Strana 64)

Transmitter

Table 4-5: Transmitter Signals

Signal Width Direction Description

Clocks and Resets

pll_ref_clk

1 Input Transceiver reference clock signal. The

reference clock selection depends on the

FPGA device family and data rate.

This signal is only applicable for V series

FPGA variants.

txlink_clk

1 Input TX link clock signal. This clock is equal to the

TX data rate divided by 40. This clock must

have the same frequency as the txphy_clk

signal but can be differential in phase due to a

different clock network.

For Subclass 1, you cannot use the output of

txphy_clk signal as txlink_clk signal . To

sample SYSREF correctly, the core PLL must

provide the txlink_clk signal and must be

configured as normal operating mode.

txlink_rst_n_reset_n

1 Input Reset for the TX link clock signal. This reset is

an active low signal.

txphy_clk[]

L Output TX parallel clock output for the TX PCS. This

clock must have the same frequency as

txlink_clk signal.

This clock is output as an optional port for

user if the txlink_clk and txframe_clk

signals are operating at the same frequency in

Subclass 0 operating mode.

tx_digitalreset[]

(22)

L Input Reset for the transceiver PCS block. This reset

is an active high signal.

tx_analogreset[]

(22)

L Input Reset for the transceiver PMA block. This

reset is an active high signal.

(22)

The Transceiver PHY Reset Controller IP Core controls this signal.

UG-01142

2015.05.04

Transmitter

4-27

JESD204B IP Core Functional Description

Altera Corporation

Send Feedback

1 2 ... 59 60 61 62 63 64 65 66 67 68 69 ... 157 158

Komentáře k této Příručce

Žádné komentáře

Altera JESD204B IP Uživatelský manuál Strana 64

Komentáře k této Příručce

Související produkty a manuály pro Měřící nástroje Altera JESD204B IP