Altera JESD204B IP Uživatelský manuál Strana 52
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- Tabulka s obsahem
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Hodnocené. / 5. Na základě hodnocení zákazníků
Figure 4-6: Subclass 0 — Combining the SYNC_N Signal for JESD204B TX IP Core
SYSREF Tied to
0 for Subclass 0
JESD204B IP Core
TX
SYSREF
SYNC_N
DEV_SYNC_N
MDEV_SYNC_N
SYSREF
SYNC_N
DEV_SYNC_N
MDEV_SYNC_N
SYSREF
SYNC_N
DEV_SYNC_N
MDEV_SYNC_N
FPGA Device
Converter Device 0
L
Converter Device 1
L
Converter Device 2
L
SYNC_N
SYNC_N
SYNC_N
Clock Chip
FPGA Reference Clock
SYNC* (1)
DAC Reference
Clock
Note:
1. SYNC* is not associated to SYNC_N in the JESD204B specification. SYNC* refers to JESD204A (Subclass 0) converter devices that
may support synchronization via additional SYNC signalling.
JESD204B IP Core
TX
JESD204B IP Core
TX
For Subclass 1 implementation, you may choose to combine or not to combine the SYNC_N signal from the
converter device. If you implement two ADC converter devices as a multipoint link and one of the
converter is unable to link up, the functional link will still operate. You must manage the trace length for
the SYSREF signal and also the differential pair to minimize skew.
The SYNC_N is the direct signal from the DAC converters. The error signaling from SYNC_N is filtered and
sent out as dev_sync_n output signal. The dev_sync_n signal from the JESD204B TX IP core must
loopback into the mdev_sync_n signal of the same instance without combining the SYNC_N signal.
Apart from that, you must set the same RBD offset value (csr_rbd_offset) to all the JESD204B RX IP
cores within the same multipoint link for the RBD release (the latest lane arrival for each of the links). The
JESD204 RX IP core will deskew and output the data when the RBD offset value is met. The total latency
is consistent in the system and is also the same across multiple resets. Setting a different RBD offset to
each link or setting an early release does not guarantee deterministic latency and data alignment.
UG-01142
2015.05.04
SYNC_N Signal
4-15
JESD204B IP Core Functional Description
Altera Corporation
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- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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