Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Uživatelský manuál Strana 373
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
AXI4-Lite Assertions
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
373
April 2014
AXI4-
60051
AXI4_AWREGION_CHANGED_BEFORE_
AWREADY
The value of AWREGION has
changed from its initial value
between the time AWVALID was
asserted and before AWREADY was
asserted.
A3.2.1
AXI4-
60052
AXI4_AWREGION_MISMATCH The AWREGION value does not
match the value defined in the region
map.
A8.2.1
AXI4-
60053
AXI4_AWREGION_UNKN AWREGION has an X
value/AWREGION has a Z value.
AXI4-
60054
AXI4_AWSIZE_CHANGED_BEFORE_
AWREADY
The value of AWSIZE has changed
from its initial value between the time
AWVALID was asserted and before
AWREADY was asserted.
A3.2.1
AXI4-
60055
AXI4_AWSIZE_UNKN AWSIZE has an X value/AWSIZE
has a Z value.
AXI4-
60056
AXI4_AWUSER_CHANGED_BEFORE_
AWREADY
The value of AWUSER has changed
from its initial value between the time
AWVALID was asserted and before
AWREADY was asserted.
A3.2.1
AXI4-
60057
AXI4_AWUSER_UNKN AWUSER has an X value/AWUSER
has a Z value.
AXI4-
60058
AXI4_AWVALID_DEASSERTED_BEFORE_
AWREADY
AWVALID has been de-asserted
before AWREADY was asserted.
A3.2.1
AXI4-
60059
AXI4_AWVALID_HIGH_ON_FIRST_
CLOCK
A master interface must begin driving
AWVALID high only at a rising clock
edge after ARESETn is HIGH.
A3.1.2
AXI4-
60060
AXI4_AWVALID_UNKN AWVALID has an X value/AWVALID
has a Z value.
AXI4-
60061
AXI4_BID_CHANGED_BEFORE_BREADY The value of BID has changed from
its initial value between the time
BVALID was asserted and before
BREADY was asserted.
A3.2.1
AXI4-
60062
AXI4_BID_UNKN BID has an X value/BID has a Z
value.
AXI4-
60063
AXI4_BREADY_NOT_ASSERTED_AFTER_
BVALID
When BVALID has been asserted
BREADY should be asserted in
config_max_latency_BVALID_assert
ion_to_BREADY clock periods.
AXI4-
60064
AXI4_BREADY_UNKN BREADY has an X value/BREADY
has a Z value.
AXI4-
60065
AXI4_BRESP_CHANGED_BEFORE_BREADY The value of BRESP has changed
from its initial value between the time
BVALID was asserted and before
BREADY was asserted.
A3.2.1
Table A-1. AXI4 Assertions (cont.)
Error
Code
Error Name Description Property
Ref
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
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