Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Uživatelský manuál Strana 213
- Strana / 413
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Mentor Verification IP AE AXI4-Lite User Guide, V10.3
213
April 2014
Chapter 9
VHDL Slave BFM
This chapter provides information about the VHDL slave BFM. The BFM has an API that
contains procedures to configure the BFM and to access the “Transaction Record” on page 28
during the lifetime of the transaction.
Slave BFM Protocol Support
The AXI4-Lite slave BFM supports the AMBA AXI4 protocol with restrictions detailed in
“Protocol Restrictions” on page 17.
Slave Timing and Events
For detailed timing diagrams of the protocol bus activity, refer to the relevant AMBA AXI
Protocol Specification chapter, which you can use to reference details of the following slave
BFM API timing and events.
The specification does not define any timescale or clock period with signal events sampled and
driven at rising ACLK edges. Therefore, the slave BFM does not contain any timescale,
timeunit, or timeprecision declarations with the signal setup and hold times specified in units of
simulator time-steps.
Slave BFM Configuration
The slave BFM supports the full range of signals defined for the AMBA AXI Protocol
Specification. The BFM has parameters that you can use to configure the widths of the address
and data signals and transaction fields to configure timeout factors, setup and hold times, and so
on.
You can change the address and data signals widths from their default settings by assigning
them new values, usually performed in the top-level module of the test bench. These new values
are then passed into the slave BFM via a parameter port list of the slave BFM component.
Table 9-1 lists the parameter names for the address and data signals, and their default values.
Note
See “Running the Qsys Tool” on page 356 for details of the Qsys Parameter Editor.
- AMBA AXI4-Lite 1
- User Guide 1
- Table of Contents 10
- List of Examples 12
- List of Figures 14
- List of Tables 15
- About This User Guide 17
- Protocol Restrictions 17
- Supported Simulators 18
- Simulator GCC Requirements 18
- Chapter 1 21
- Mentor VIP Altera Edition 21
- What Is a Transaction? 22
- AXI4-Lite Transactions 22
- Chapter 2 27
- SystemVerilog API Overview 27
- Chapter 3 39
- SystemVerilog Master BFM 39
- SystemVerilog Master API 43
- Returns 44
- Example 58
- Chapter 4 63
- SystemVerilog Slave BFM 63
- SystemVerilog Slave API 68
- Arguments config_name 69
- Chapter 5 91
- SystemVerilog Monitor API 96
- Prototype 100
- Arguments 100
- April 2014 102
- SystemVerilog Monitor BFM 105
- Helper Functions 111
- SystemVerilog Tutorials 115
- Chapter 6 115
- BFM Master Test Program 116
- Verifying a Slave DUT 117
- Verifying a Master DUT 123
- Basic Slave API Definition 124
- *_valid_delay = 4 127
- *_ready_delay = 2 127
- Advanced Slave API Definition 129
- Initial Block 131
- Chapter 7 137
- VHDL API Overview 137
- Test Program VHDL 138
- Configuration 139
- Creating Transactions 139
- Transaction Definition 140
- Executing Transactions 144
- Waiting Events 145
- Access Transaction Record 146
- Operation Mode 147
- Channel Handshake Delay 147
- Handshake Delay 148
- Transaction Done 149
- Chapter 8 151
- VHDL Master BFM 151
- Master BFM Protocol Support 152
- Master Timing and Events 152
- Master BFM Configuration 152
- Master Assertions 155
- VHDL Master API 156
- Chapter 9 213
- VHDL Slave BFM 213
- Slave BFM Configuration 214
- Slave Assertions 216
- VHDL Slave API 217
- Operational 223
- Transaction 223
- Chapter 10 279
- VHDL Monitor BFM 279
- Monitor BFM Configuration 280
- Monitor Assertions 282
- VHDL Monitor API 283
- Chapter 11 335
- VHDL Tutorials 335
- BFM Slave Test Program 341
- Chapter 12 353
- Running the Qsys Tool 356
- Running a Simulation 359
- ModelSim Simulation 360
- Editing the modelsim.ini File 363
- Questa Simulation 364
- Cadence IES Simulation 364
- Synopsys VCS Simulation 366
- Appendix A 369
- AXI4-Lite Assertions 384
- Appendix B 385
- SystemVerilog Test Programs 385
- Appendix C 397
- VHDL Test Programs 397
- End-User License Agreement 409
Související produkty a manuály pro Měřící nástroje Altera Mentor Verification IP Altera Edition AMBA AXI4-Li
Měřící nástroje Altera Mentor Verification IP Altera Edition AMBA AXI4-St Uživatelský manuál
(231 stránky)
(231 stránky)
Měřící nástroje Altera Nios II Uživatelský manuál
(22 stránky)
(22 stránky)
Měřící nástroje Altera Nios II Uživatelský manuál
(22 stránky)
(22 stránky)
Měřící nástroje Altera Mentor Verification IP Altera Edition AMBA AXI3/4T Uživatelský manuál
(783 stránky)
(783 stránky)
Měřící nástroje Altera PCI Development Kit, Cyclone II Edition Getting St Uživatelský manuál
(40 stránky)
(40 stránky)
Měřící nástroje Altera PCI Express Development Kit, Stratix II GX Edition Uživatelský manuál
(36 stránky)
(36 stránky)
Měřící nástroje Altera PowerPlay Early Power Estimator for Altera CPLDs Uživatelský manuál
(30 stránky)
(30 stránky)
Měřící nástroje Altera PCI Compiler Uživatelský manuál
(360 stránky)
(360 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.056 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce