Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Uživatelský manuál stáhnout pdf (Strana 342)

Mentor Verification IP AE AXI4-Lite User Guide, V10.3

342

VHDL Tutorials

Verifying a Master DUT

April 2014

do_byte_read()

The do_byte_read() procedure reads a data byte from the Internal Memory mem given an

address location addr, as shown below.

You can edit this procedure to modify the way the read data is extracted from the internal

memory.

-- Procedure : do_byte_read

-- Procedure to provide read data byte from memory at particular input

-- address

procedure do_byte_read(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1

downto 0); data : out std_logic_vector(7 downto 0)) is

begin

data := mem(to_integer(addr));

end do_byte_read;

do_byte_write()

The do_byte_write() procedure when called writes a data byte to the Internal Memory mem

given an address location addr, as shown below.

You can edit this procedure to modify the way the write data is stored in the internal memory.

-- Procedure : do_byte_write

-- Procedure to write data byte to memory at particular input address

procedure do_byte_write(addr : in std_logic_vector(AXI4_MAX_BIT_SIZE-1

downto 0); data : in std_logic_vector(7 downto 0)) is

begin

mem(to_integer(addr)) := data;

end do_byte_write;

m_wr_addr_phase_ready_delay

The m_wr_addr_phase_ready_delay variable holds the AWREADY signal delay. The delay

value extends the length of the write address phase by a number of ACLK cycles. The starting

point of the delay is determined by the assertion of the AWVALID signal.

Example 11-8 shows the AWREADY signal delayed by two ACLK cycles. You can edit this

variable to change the AWREADY signal delay.

Example 11-8. m_wr_addr_phase_ready_delay

-- Variable : m_wr_addr_phase_ready_delay

signal m_wr_addr_phase_ready_delay : integer := 2;

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Altera Mentor Verification IP Altera Edition AMBA AXI4-Li Uživatelský manuál Strana 342