Altera Low Latency Ethernet 10G MAC Uživatelský manuál Strana 64
- Strana / 109
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Word
Offset
Register Name Description Access HW Reset
Value
0x0058 pfc_holdoff_quanta_0
(5)
Specifies the gap between two consecutive
transmissions of XOFF pause frames in unit
of quanta, 1 unit = 512 bits time. The gap
prevents back-to-back transmissions of
pause frames, which may affect the
transmission of data frames.
• Bits 15:0— pfc_holdoff_quanta_
n[15:0] specifies the gap for priority
queue n.
• Bits 31:16—reserved.
Configure these registers before you enable
the MAC IP core for operations.
RW 0x1
0x0059 pfc_holdoff_quanta_1
(5)
0x005A pfc_holdoff_quanta_2
(5)
0x005B pfc_holdoff_quanta_3
(5)
0x005C pfc_holdoff_quanta_4
(5)
0x005D pfc_holdoff_quanta_5
(5)
0x005E pfc_holdoff_quanta_6
(5)
0x005F pfc_holdoff_quanta_7
(5)
Unidirectional Control Registers
Table 4-8: Unidirectional Control Registers
Word
Offset
Register Name Description Access HW Reset
Value
0x0070 tx_unidir_control
(6)
• Bit 0—configures unidirectional feature on
the TX path.
0: Disables unidirectional feature.
1: Enables unidirectional feature.
• Bit 1—configures remote fault sequence
generation when unidirectional feature is
enabled on the TX path.
0: Enable remote fault sequence generation
on detecting local fault.
1: Disable remote fault sequence generation.
• Bits 31:2—reserved.
Configure this register before you enable the
MAC IP core for operations.
RW
0x0
(6)
This register is used when you turn on Enable unidirectional feature. It is reserved when not used.
4-12
Unidirectional Control Registers
UG-01144
2014.12.15
Altera Corporation
Configuration Registers for LL Ethernet 10G MAC
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
Související produkty a manuály pro Měřící nástroje Altera Low Latency Ethernet 10G MAC
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(3 stránky)
(3 stránky)
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(80 stránky)
(80 stránky)
Měřící nástroje Altera SCFIFO Uživatelský manuál
(28 stránky)
(28 stránky)
Měřící nástroje Altera Serial Digital Interface (SDI) MegaCore Function Uživatelský manuál
(140 stránky)
(140 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.026 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce