Altera Low Latency Ethernet 10G MAC Uživatelský manuál Strana 33
- Strana / 109
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Figure 3-10: Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode Enabled
The following diagram shows back-to-back transmission of normal frames with preamble passthrough
mode enabled.
tx_312_5_clk
avalon_st_tx_startofpacket
avalon_st_tx_valid
avalon_st_tx_ready
avalon_st_tx_endofpacket
avalon_st_tx_error
avalon_st_tx_empty[1:0]
avalon_st_tx_data[31:0]
xgmii_tx_data[31:0]
xgmii_tx_control[3:0]
avalon_st_tx_data[31:24]
avalon_st_tx_data[23:16]
avalon_st_tx_data[15:8]
avalon_st_tx_data[7:0]
xgmii_tx_data[7:0]
xgmii_tx_data[15:8]
xgmii_tx_data[23:16]
xgmii_tx_data[31:24]
* * * * * * * ** * *3 ac8b_600d* * * * * * * * ** * * * * * * * ** * * * * * * * **
*
* * * * **
*
aa2f_4bbd **
*
*
* * * * * * * ** * * * *707 *b * * * * * **0 * * * * * * * ** * * * * * * * **
*
* * * * ** **707
*
** * * * * **b
0 f 1 0 1f
0
e
6f de b3 23 32 5f 00 3b89 a5 00 ac0b 71 a0 90 c9 4c f0 6c a461 f9 36 22 1a 21 b7 f3 bca3 69 30 fa 2e a9 87 bb dbf5
b5
84 22 ff 64 6700
4d
aa 2cea
c8
7a
2b d2 b4 5f 1f 37 23 05ab 1b ff 8b7e d3 bc 59 b0 db 15 ae ade2 02 0f 21 62 74 c0 36 c8 13 d9 12 15 f0 a4 00da
45
f9 37 ff bd 03ac
53
2f 4b81
e7
04
25 d4 48 e9 ad a5 45 e3f0 8f b7 60fa da d7 38 0f a9 60 be 344d 83 d4 8c68 5d e0 c1 26 74 95 65 ac ce 0079
85
e7 8a 5d f53b
ba
4b eb97
24
0df8 eb6e ff 03
89 8d 93 66 3a d5 67 62 94 f3 0d9c ee 3f 2c 44 d5 ca 11 6c85 4e 7b 26 64 d8 e7 0a 19 a4 5c 9e b0 004a
40
0a d5 5b a850
83
bd ce94
48
57 03bc ff 225e 48
fe 8d ad 56 98 fb 8f 50b3 6f de b3 07 fb 5f 00 89 3b a5 0b00 71 a0 90 c9 4c f0 6c a461 f9 30 22 1a 21 b7 f3 bca3
84
7a 69 2e 87a9
bb
fb07
22
ac23 4a fd 30 fa dbf5
7e
8d b9 81 16 88 54 ac b3fc 2b d2 b4 07 1f 37 23 ab 05 1b 7eff d3 bc 59 b0 db 15 ae ade2 02 0f 21 62 74 c0 36
f9
04 c8 12 f015
a4
4507
37
8b5f a6 13 d9 f4da
fd
2b 0f 49 ca 38 40 9f f814 25 d4 48 07 ad a5 45 f0 e3 8f fab7 da d7 38 0f a9 60 be 344d 83 d4 68 5d 8c e0 eb6e
e7
0d c1 95 ac65
ce
8507
8a
60e9 0a 26 74 0f79
d6 38 84 f0 3a 76 7f c59c 89 8d 93 07 3a d5 67 62 94 9cf3 ee 3f 2c 44 d5 ca 11 6c85 4e 7b 26 64 d8 03bc
0a
57 e7 a4 9e5c
b0
4007
d5
0d66 e7 0a 19 ce4a5e 48
Figure 3-11: Error Condition—Underflow
The following diagrams show an underflow on the transmit datapath followed by the transmission of a
normal frame.
0
c990_2f08
0
0707_0707
f 00f
*c61
*0707
97
36
6c
61
c9
90
2f
08
fc
07
07
07
07
07
07
07
07
tx_312_5_clk
avalon_st_tx_startofpacket
avalon_st_tx_valid
avalon_st_tx_ready
avalon_st_tx_endofpacket
avalon_st_tx_error
avalon_st_tx_empty[1:0]
avalon_st_tx_data[31:0]
xgmii_tx_data[31:0]
xgmii_tx_control[3:0]
avalon_st_tx_data[31:24]
avalon_st_tx_data[23:16]
avalon_st_tx_data[15:8]
avalon_st_tx_data[7:0]
xgmii_tx_data[7:0]
xgmii_tx_data[15:8]
xgmii_tx_data[23:16]
xgmii_tx_data[31:24]
pulse_tx_udf_errcnt
An underflow happens in the middle of a frame that results in a premature termination on the XGMII.
The remaining data from the Avalon-ST transmit interface is still received after the underflow but the
data is dropped. The transmission of the next frame is not affected by the underflow.
UG-01144
2014.12.15
TX Timing Diagrams
3-11
Functional Description of LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
Související produkty a manuály pro Měřící nástroje Altera Low Latency Ethernet 10G MAC
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(3 stránky)
(3 stránky)
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(80 stránky)
(80 stránky)
Měřící nástroje Altera SCFIFO Uživatelský manuál
(28 stránky)
(28 stránky)
Měřící nástroje Altera Serial Digital Interface (SDI) MegaCore Function Uživatelský manuál
(140 stránky)
(140 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.108 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce