Altera Low Latency Ethernet 10G MAC Uživatelský manuál Strana 63
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Hodnocené. / 5. Na základě hodnocení zákazníků
Word
Offset
Register Name Description Access HW Reset
Value
0x0044 tx_pauseframe_enable
• Bit 0—configures the transmission of
pause frames. This bit affects pause
frame requests from both register and
vector settings.
0: Disables pause frame transmission.
1: Enables pause frame transmission, if
TX path is enabled by tx_packet_
control.
• Bits 2:1—specifies the trigger for pause
frame requests.
00: Accepts pause frame requests only
from vector setting, avalon_st_pause_
data.
01: Accepts pause frame requests only
from register setting, tx_pauseframe_
control.
10 / 11: Reserved.
• Bits 31:3—reserved.
Configure this register before you enable
the MAC IP core for operations.
RW
0x1
0x0046 tx_pfc_priority_enable
(5)
Enables priority-based flow control on the
TX datapath.
• Bits 7:0—setting bit n enables priority-
based flow control for priority queue n.
For example, setting tx_pfc_priority_
enable[0] enables queue 0.
• Bits 31:8—reserved.
Configure this register before you enable
the MAC IP core for operations.
RW 0x0
0x0048 pfc_pause_quanta_0
(5)
Specifies the pause quanta for each priority
queue.
• Bits 15:0—pfc_pause_quanta_n[15:0]
specifies the pause length for priority
queue n in quanta unit, where 1 unit =
512 bits time.
• Bits 31:16—reserved.
Configure these registers before you enable
the MAC IP core for operations.
RW 0x0
0x0049 pfc_pause_quanta_1
(5)
0x004A pfc_pause_quanta_2
(5)
0x004B pfc_pause_quanta_3
(5)
0x004C pfc_pause_quanta_4
(5)
0x004D pfc_pause_quanta_5
(5)
0x004E pfc_pause_quanta_6
(5)
0x004F pfc_pause_quanta_7
(5)
(5)
This register is used only when you turn on the Enable preamble pass-through mode option. It is reserved
when not used.
UG-01144
2014.12.15
Flow Control Registers
4-11
Configuration Registers for LL Ethernet 10G MAC
Altera Corporation
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- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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