Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Uživatelský manuál stáhnout pdf (Strana 83)

cumulative count of the payload bytes in the qualifying transmitted frames, and complies with section

5.2.2.18 of the IEEE Standard 802.3-2008.

To support payload size checking per frame, the LL 40-100GbE IP core provides an octetOK count

interface instead of standard increment vectors. For most purposes, the number of payload bytes per

frame is of more interest than the cumulative count, and an increment vector that pulses when the

counter increments would be difficult to track. For each of these two registers, the IP core maintains two

signals. A 16-bit signal provides a count of the payload bytes in the current frame, and the other signal

pulses to indicate when the first signal is valid. The per-frame count is valid only when the valid signal is

asserted. All signals in this interface are functional even if you do not turn on the corresponding statistics

module.

Table 3-10: OctetOK Count Interface Signals

The signals for received frames are clocked by the clk_rxmac clock. The signals for transmitted frames are clocked

by the clk_txmac clock.

Name Signal

Direction

Description

tx_inc_

octetsOK[15:0]

Output

When tx_inc_octetsOK_valid is asserted, tx_inc_octetsOK[15:0]

holds the count of payload bytes in the current valid frame.

tx_inc_octetsOK_

valid

Output

Pulses to indicate that tx_inc_octetsOK[15:0] currently holds the

number of payload bytes for the current transmitted frame, and that

the current frame is a qualifying frame. A qualifying frame has no FCS

errors, no oversized error, no undersized error, and no payload length

error.

rx_inc_

octetsOK[15:0]

Output

When rx_inc_octetsOK_valid is asserted, rx_inc_octetsOK[15:0]

holds the count of payload bytes in the current valid frame.

rx_inc_octetsOK_

valid

Output

Pulses to indicate that rx_inc_octetsOK[15:0] currently holds the

number of payload bytes for the current received frame, and that the

current frame is a qualifying frame. A qualifying frame has no FCS

errors, no oversized error, no undersized error, and no payload length

error.

1588 Precision Time Protocol Interfaces

If you turn on Enable 1588 PTP, the Low Latency 40-100GbE IP core processes and provides 1588

Precision Time Protocol (PTP) timestamp information as defined in the IEEE 1588-2008 Precision Clock

Synchronization Protocol for Networked Measurement and Control Systems Standard.

1588 PTP packets carry timestamp information. The Low Latency 40-100GbE IP core updates the

incoming timestamp information in a 1588 PTP packet to transmit a correct updated timestamp with the

data it transmits on the Ethernet link, using a one-step or two-step clock.

The IP core connects to a time-of-day (TOD) module that continuously provides the current time of day

based on the input clock frequency. Because the module is outside the LL 40-100GbE IP core, you can use

the same module to provide the current time of day for multiple modules in your system.

Related Information

• External Time-of-Day Module for Variations with 1588 PTP Feature on page 2-20

3-38

1588 Precision Time Protocol Interfaces

UG-01172

2015.05.04

Altera Corporation

Functional Description

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