Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Uživatelský manuál Strana 39
- Strana / 196
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Figure 2-7: Typical 40GbE Traffic on the Avalon-ST Interface
Shows typical traffic from the simulation testbench created using the run_vsim.do script in ModelSim. In
this case the IP core is a 40GbE IP core with adapters. In Stratix V variations the script is found in
<instance_name>_example_design/alt_eth_ultra/example_testbench/run_vsim.do and in Arria 10 variations
the script is found in <example_design_directory>/example_testbench/run_vsim.do.
Note: Client logic must maintain the l4_tx_valid signal asserted while asserting SOP, through the
assertion of EOP. Client logic should not pull this signal low during a packet transmission.
l4_tx_data[255:0]
l4_tx_empty[4:0]
l4_tx_startofpacket
l4_tx_endofpacket
l4_tx_ready
l4_tx_valid
l4_rx_data[255:0]
l4_rx_startofpacket
l4_rx_endofpacket
l4_rx_valid
l4_rx_empty[4:0]
B8 . B8 . B8 . B87B0031B8 . 57 . 57 . 57 . 57 . 573500 . 5735004 . 57350055573500545735005357
00 02 00 01
65F300 .. 65F301 . 65F301 . 65F301 . FA . FAAB00 . FAAB00 . FAAB00 . FAAB00 . 61 . 61A000 .
14
1D
1 2
3 4
6 8 975
The markers in the figure show the following sequence of events:
1. At marker 1, the application asserts l4_tx_startofpacket, indicating the beginning of a TX packet.
2. At marker 2, the application asserts l4_tx_endofpacket, indicating the end of the TX packet. The
value on l4_tx_empty[4:0] indicates that the 2 least significant bytes of the last data cycle are empty.
3. At marker 3, the IP core asserts l4_rx_startofpacket, indicating the beginning of an RX packet. A
second transfer has already started on the TX bus.
4. At marker 4, the 40GbE IP core deasserts l4_rx_valid, indicating that the IP core does not have new
valid data to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains unchanged for a
second cycle, but because the l4_rx_valid signal is deasserted, the client should ignore the value on
the RX signals.
5. A marker 5, the 40GbE IP core asserts l4_rx_valid, indicating that it has valid data to send to the
client on l4_rx_data[255:0].
6. At marker 6, the 40GbE IP core deasserts l4_rx_valid, indicating that it does not have new valid data
to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains unchanged for a second
cycle.
UG-01172
2015.05.04
Low Latency 40-100GbE IP Core Testbench Overview
2-25
Getting Started
Altera Corporation
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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