Altera Low Latency 40-Gbps Ethernet MAC and PHY MegaCore Uživatelský manuál Strana 18
- Strana / 196
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
1. In the IP Catalog (Tools > IP Catalog), select a target device family.
2. In the IP Catalog, locate and double-click the name of the IP core to customize. The New IP Variation
window appears.
3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation
settings in a file named <your_ip>.qsys (for Arria 10 variations) or <your_ip>.qip (for Stratix V
variations).
4. If your IP core targets the Arria 10 device family, you must select a specific device in the Device field.
The example project overwrites the selection with the device on the target board. However, if you do
not select a specific device, the Quartus II software does not generate your IP core correctly.
5. Click OK. The parameter editor appears.
6. Specify the parameters and options for your IP variation in the parameter editor, including one or
more of the following. Refer to your IP core user guide for information about specific IP core
parameters.
• Specify parameters defining the IP core functionality, port configurations, and device-specific
features.
• Specify options for processing the IP core files in other EDA tools.
7. For Arria 10 variations, follow these steps:
a. Optionally, to generate a simulation testbench or example project, follow the instructions in
Generating the Low Latency 40-100GbE Testbench on page 2-28.
b. Click Generate HDL. The Generation dialog box appears.
c. Specify output file generation options, and then click Generate. The IP variation files generate
according to your specifications.
d. Click Finish. the parameter editor adds the top-level .qsys file to the current project automatically.
If you are prompted to manually add the .qsys file to the project, click Project > Add/Remove Files
in Project to add the file.
8. For Stratix V variations, follow these steps:
a. Click Finish.
b. Optionally, to generate a simulation testbench or example project, follow the instructions in
Generating the Low Latency 40-100GbE Testbench on page 2-28.
After you click Finish and optionally follow the additional step to generate a simulation testbench
and example project, if available for your IP core variation, the parameter editor adds the top-
level .qsys file or top-level .qip file to the current project automatically. If you are prompted to
manually add the .qip file to the project, click Project > Add/Remove Files in Project to add the
file.
9. After generating and instantiating your IP variation, make appropriate pin assignments to connect
ports.
2-4
Specifying the Low Latency 40-100GbE IP Core Parameters and Options
UG-01172
2015.05.04
Altera Corporation
Getting Started
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Features 6
- Device Family Support 8
- IP Core Verification 9
- Simulation Environment 10
- Compilation Checking 10
- Hardware Testing 10
- Variation 11
- A B C D E F 11
- Parameter 11
- Release Information 14
- Getting Started 15
- OpenCore Plus IP Evaluation 17
- IP Core Parameters 19
- Parameter Type Range Default 23
- Parameter Description 23
- File Name Description 29
- Pin Assignments 32
- External TX MAC PLL 35
- File Names Description 38
- Initializing the IP Core 45
- Functional Description 46
- High Level System Overview 47
- Address Insertion 49
- Length/Type Field Processing 49
- Frame Padding 50
- Client Interface 51
- Data Bus Width (Bits) 51
- Three unusable words 57
- Order of Transmission 59
- RX CRC Forwarding 63
- Inter-Packet Gap 63
- Pause Ignore 63
- Control Frame Identification 64
- Name Direction Description 65
- Low Latency 100GbE CAUI–4 PHY 72
- External Transceiver PLL 72
- Pause Control Frame Filtering 76
- Statistics Counters Interface 79
- Name Signal 80
- Direction 80
- Description 80
- OctetOK Count Interface 82
- Transparent Clock Mode 85
- PTP Receive Functionality 87
- PTP Transmit Functionality 88
- 1588 PTP Interface Signals 90
- PTP Timestamp Formats 92
- PHY Status Interface 93
- Control and Status Interface 94
- Signal Name Description 97
- UG-01172 100
- 2015.05.04 100
- Related Information 108
- Software Interface: Registers 109
- PHY Registers 112
- LL 40GBASE-KR4 Registers 116
- Pause Registers 130
- TX Statistics Registers 137
- RX Statistics Registers 143
- 1588 PTP Registers 148
- Ethernet Glossary 150
- Term Definition 151
- Altera Corporation 153
- Send Feedback 153
- Arria 10 10GBASE-KR Registers 160
- 0x4D6 to 181
- MAC+PHY KR solution 181
- Subscribe 182
- Additional Information 187
- Date Compatible ACDS 188
- How to Contact Altera 194
- Typographic Conventions 195
- Visual Cue Meaning 196
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