Altera ALTPLL (Phase-Locked Loop) IP Core Uživatelský manuál stáhnout pdf (Strana 4)

The following list describes the operation modes for the ALTPLL IP core:

• Normal mode—The PLL feedback path source is a global or regional clock network, minimizing clock

delay to registers for that clock type and specific PLL output. You can specify PLL output that is

compensated in normal mode.

• Source-Synchronous mode—The data and clock signals arrive at the same time at the data and clock

input pins. In this mode, the signals are guaranteed to have the same phase relationship at the clock and

data ports of any Input Output Enable register.

• Zero-Delay Buffer mode—The PLL feedback path is confined to the dedicated PLL external clock output

pin. The clock port driven off-chip is phase aligned with the clock input for a minimal delay between the

clock input and the external clock output.

• No Compensation mode—The PLL feedback path is confined to the PLL loop. It has no clock network

or other external source. A PLL in no-compensation mode has no clock network compensation, but clock

jitter is minimized.

• External Feedback mode—The PLL compensates for the fbin feedback input to the PLL. The delay

between the input clock pin and the feedback clock pin is minimized.

Operation Modes Supported in Each Device Family

The following table summarizes the operation modes supported for each device family.

Table 2: PLL Types and Modes Supported in Different Device Families

External FeedbackNo CompensationZero-Delay BufferSource-

Synchronous

NormalDevice Family

Enhanced PLLAll PLL typesEnhanced PLLAll PLL typesAll PLL typesArria GX

—Left_Right PLLLeft_Right PLLLeft_Right PLLLeft_Right PLLArria II GX

All PLL typesAll PLL typesAll PLL typesAll PLL typesAll PLL typesStratix IV

Enhanced PLLAll PLL typesEnhanced PLLAll PLL typesAll PLL typesStratix III

Enhanced PLLAll PLL typesEnhanced PLLAll PLL typesAll PLL typesStratix II

Enhanced PLLAll PLL typesEnhanced PLLAll PLL typesAll PLL typesStratix II GX

Enhanced PLLAll PLL typesEnhanced PLL—All PLL typesStratix

Enhanced PLLAll PLL typesEnhanced PLL—All PLL typesStratix GX

—All PLL typesAll PLL typesAll PLL typesAll PLL typesCyclone IV

—All PLL typesAll PLL typesAll PLL typesAll PLL typesCyclone III

—All PLL typesAll PLL typesAll PLL typesAll PLL typesCyclone II

—All PLL typesAll PLL types—All PLL typesCyclone

Parameter Settings

Describes how to set the operation mode for the PLL using the ALTPLL parameter editor. The parameter

settings are located on the General/Modes page of the ALTPLL parameter editor.

ALTPLL (Phase-Locked Loop) IP Core User Guide

Altera Corporation

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Operation Modes Supported in Each Device Family

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Altera ALTPLL (Phase-Locked Loop) IP Core Uživatelský manuál Strana 4