Altera ALTPLL (Phase-Locked Loop) IP Core Uživatelský manuál Strana 1

ALTPLL (Phase-Locked Loop) IP Core User Guide2014.08.18ug-altpllSubscribeSend FeedbackThe Altera Phase-Locked Loop (ALTPLL) IP core implements phase l

Each option has the following two columns:• Requested settings• Actual settingsThe requested settings are the settings that you want to implement, and

Select Use these clock settings for the DPA clock if you want the output clock signal of the PLL to drivethe input clock port of the DPA block in the

Cyclone Series PLLFast PLLEnhanced PLLLeft_RightTop_BottomDevice Family—46——Stratix II GX—36(1)——Stratix—36(1)——Stratix GX5————Cyclone IV5————Cyclone

You should include the areset signal in your designs if any of the following conditions hold:• PLL reconfiguration or clock switchover is enabled in y

Supported Advanced SignalsDevice FamilyaresetpfdenapllenaYesYesYesStratix GXYesYes—Cyclone IVYesYes—Cyclone IIIYesYesYesCyclone IIYesYesYesCycloneCloc

Figure 9: Clock SwitchoverTo enable the switchover feature, turn on Create an 'inclk1' input for a second input clock, and specify thefreque

Summary of Automatic Clock Switchover FeatureThe following table summarizes automatic clock switchover support in the supported device families. Alsos

Cyclone Series PLLFast PLLEnhanced PLLLeft_RightTop_BottomDeviceYes————Cyclone IIIYes————Cyclone IINo————CycloneSpread-Spectrum ClockingSpread-spectru

The modulation frequency, often called sweep rate, defines how fast the spreading signal sweeps from theminimum to the maximum frequency.Turning on sp

use a gated lock signal. A gated locked signal or an ungated locked signal can feed a logic array or an outputpin. When you must reset the gated count

Building Blocks of a PLLFigure 1: PLL Block DiagramFeedbackNPost-DividersKLoopFilter& VCOChargePumpPFDVMFINFREFFVCOFOUT1FOUT1FOUT2The PLL consists

The following figure shows the Hold Locked Output option.Figure 13: Hold Locked Output OptionCalculating the Value of Gated Lock CounterTo calculate t

you to configure the characteristics of the PLL loop filter. Most loop filters contain only passive components,such as resistors and capacitors, which

Table 11: Programmable Bandwidth SupportCyclone Series PLLFast PLLEnhanced PLLLeft_RightTop_BottomDevice Family—YesYes——Arria GX———Yes(4)—Arria II GX—

The parameter settings to generate output files using advanced PLL parameters are located on theScan/Inputs/Lock or Inputs/Lock page of the ALTPLL par

Figure 16: Dynamic Reconfiguration Options for Stratix and Stratix GX DevicesThe following table lists the dynamic reconfiguration options using scan

Figure 17: Dynamic Reconfiguration Options Using Configuration FilesThe following table lists the normal dynamic reconfiguration scheme options.Table

Cyclone Series PLLFast PLLEnhanced PLLLeft_RightTop_BottomDevice Family———YesYesStratix IV———YesYesStratix III—YesYes——Stratix II—YesYes——Stratix II G

Parameter SettingsThe parameter settings to enable the dynamic phase configuration feature are located on the PLLReconfiguration page of the ALTPLL pa

When using Advanced Parameters, the PLL wrapper file (<ALTPLL_instantiation_name>.v|.vhd) iswritten in a format that allows you to identify the

Customizing and Generating IP CoresYou can customize IP cores to support a wide variety of applications. The Quartus II IP Catalog and parametereditor

Parameter SettingYou select the PLL type on the General/Modes page of the ALTPLL parameter editor. The list of availablePLL types to choose from depen

Figure 21: Quartus II IP CatalogSearch and filter IP for your target deviceDouble-click to customize, right-click for informationThe IP Catalog is als

Figure 22: IP Parameter EditorsView IP portand parameterdetailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targe

Specifying IP Core Parameters and Options (Legacy Parameter Editors)The Quartus II software version 14.0 and previous uses a legacy version of the par

Figure 24: IP Core Generated FilesNotes:1. If supported and enabled for your IP variation2. If functional simulation models are generated3. Ignore thi

Figure 25: Simulation in Quartus II Design FlowPost-fit timingsimulation netlistPost-fit timingsimulation (3)Post-fit functionalsimulation netlistPost

Table 15: IP Core Upgrade StatusCorrective ActionIP Core StatusYou must upgrade the IP variation before compiling in the current version ofthe Quartus

Figure 26: Upgrading IP CoresDisplays upgradestatus for all IP coresin the ProjectUpgrades all IP core that support “Auto Upgrade”Upgrades individual

Related InformationAltera IP Release NotesMigrating IP Cores to a Different DeviceIP migration allows you to target the latest device families with IP

Ports and ParametersThe ALTPLL IP core ports and parameters are available to customize the ALTPLL IP core according to yourapplication.The options you

DescriptionConditionPort Name(6)The control input port todynamically toggle between clockinput ports (inclk0 and inclk1ports), or to manually override

The following list describes the operation modes for the ALTPLL IP core:• Normal mode—The PLL feedback path source is a global or regional clock netwo

DescriptionConditionPort Name(6)Enables the phase frequencydetector (PFD). When the PFD isdisabled, the PLL continues tooperate regardless of the inpu

DescriptionConditionPort Name(6)Clock enable port for the serialscan chain. Available only forArria II GX, Cyclone III,HardCopy III, and Stratix IIIde

DescriptionConditionPort Name(7)clkbad1 and clkbad0 ports checkfor input clock toggling. If theinclk0 port stops toggling, theclkbad0 port goes high.

DescriptionConditionPort Name(7)The port that feeds the fbin portthrough the mimic circuitry. If afeedback path is not connected,the compiler automati

DescriptionConditionPort Name(7)This output port acts as anindicator when the PLL hasreached phase-locked. The lockedport stays high as long as the PL

DescriptionConditionPort Name(7)The data output for the serial scanchain. You can use thescandataout port to determinewhen PLL reconfiguration iscompl

ALTPLL Bidirectional PortTable 18: ALTPLL Bidirectional Output PortDescriptionConditionPort NameThe bidirectional port thatconnects to the mimic circu

DescriptionTypeParameterSpecifies the initial value for the corresponding counter,C[9..0]. If omitted, default is 1. Counters C[9..5] arenot available

DescriptionTypeParameterSpecifies the integer multiplication factor for the VCOfrequency for the corresponding output clock port,CLK[9..0]. The parame

DescriptionTypeParameterSpecifies the output clock port which should becompensated for.• If the OPERATION_MODE parameter is set to normalmode, the val

The following figure shows the options you can select from the page.Figure 2: Operation Mode OptionsThe following table lists the options you can sele

DescriptionTypeParameterSpecifies the external counter for the correspondingexternal clock output port, EXTCLK[3..0]. Values are E0,E1, E2, or E3. If

DescriptionTypeParameterSpecifies which clock output has a board-level connectionto the fbin port. If the OPERATION_MODE parameter is setto EXTERNAL_F

DescriptionTypeParameterSpecifies the high period count for the correspondingL[1..0] counter. Values range from 1 to 512. If omitted,the default is 1.

DescriptionTypeParameterSpecifies the modulus for the M counter. Provides directaccess to the internal PLL parameters. If the M parameteris specified,

DescriptionTypeParameterStringOPERATION_MODEALTPLL (Phase-Locked Loop) IP Core User GuideAltera CorporationSend Feedbackug-altpllALTPLL Parameters5420

DescriptionTypeParameterSpecifies the operation of the PLL. Values are EXTERNAL_FEEDBACK, NO_COMPENSATION, NORMAL, ZERO_DELAY_BUFFER, and SOURCE_SYNCH

DescriptionTypeParameterthe compensated clock output port of a PLL in source-synchronous mode.This parameter is ignored if it is applied to anything o

DescriptionTypeParameterSpecifies the EXTCLK[3..0] port connectivity. Values arePORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.Strin

DescriptionTypeParameterSpecifies the SCANCLK port connectivity. Values are PORT_USED or PORT_UNUSED. If omitted, the default is PORT_UNUSED.StringPOR

DescriptionTypeParameterSpecifies, in picoseconds (ps), the phase shift for thecorresponding sclkout[1..0] port. The maximum phasevalue is 7/8 of one

Figure 3: General OptionsThe following table lists the options you can select from the page.Table 4: Operation Mode Options and DescriptionsDescriptio

DescriptionTypeParameterSpecifies whether the fbmimicbidir port is used. Valuesare ON or OFF. If omitted, the default is OFF.For Stratix III and Strat

DescriptionTypeParameterSpecifies the minimum value for the VCO pin. Use forsimulation purposes only.IntegerVCO_MINSpecifies the integer multiplicatio

• ddr-clk-msim.zip• shift_clk.zip• shift_clk_msim.zipDesign Example 1: Differential ClockThis design example uses the ALTPLL IP core to generate an ex

16. Turn on Use this clock.17. Turn on Enter output clock parameters, and in the Clock multiplication factor box, type 5.18. In the Clock division fac

The ddr_clk design is now implemented.Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera SoftwareThis ModelSim design example is

Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted ClocksTo generate 133-MHz, 200-MHz, and 200-MHz time-shifted clocks, follow these steps:Before y

c.For Clock multiplication factor, type 2.d.For Clock division factor, type 1.e.For Clock phase shift, type 0.00 and select ns.f.For Clock duty cycle

Figure 30: ALTPLL shift_pll Design SchematicImplementing the shift_clk DesignTo assign the EP1S10F780C5 device to the project and compile the project,

4. On the File menu, click Save.5. Start the ModelSim-Altera software.6. On the File menu, click Change Directory.7. Select the folder in which you un

Changes MadeVersionDate• Updated the following sections:• “Device Family Support” section• “Introduction” section• “Features” section• “General Descri

To extract valid parameter values to maximize your PLL lock range, perform the following steps:1. In the schematic editor, double-click the ALTPLL ins

ValueOptionc2This clock signal is the slowclock signal that feeds thesynchronization register of theALTLVDS IP core.Output frequency = data rate/deser

Output ClocksThe PLL can generate a number of clock output signals depending on the PLL type and the device familythat you select in the ALTPLL parame