Altera SerialLite II IP Core Uživatelský manuál Strana 83
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Chapter 4: Functional Description 4–29
Signals
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Table 4–10 shows the troubleshooting signals. These signals do not necessarily need to
be connected to external logic. In general, they are for diagnostic purposes. Some
signals in Table 4–10 are only available in certain configurations.
Table 4–10. Troubleshooting Signals (Part 1 of 2)
Signal Direction Clock Domain Description
stat_tc_rst_done
Output
tx_coreclock
Reset controller logic
Done
signal. When
high, the reset controller has completed the
ALTGXB reset sequence successfully.
err_rr_foffre_oflw
(1)
Output
rrefclk
Indicates that frequency offset tolerance FIFO
buffer has overflowed. The link restarts.
stat_tc_foffre_empty
(1)
Output
tx_coreclock
Indicates that frequency offset tolerance FIFO
buffer has underflowed. The link does not go
down. IDLE characters are inserted. This
does not have a negative impact on the core,
and is simply for diagnostic purposes.
stat_rr_ebprx
(1)
Output
rrefclk
Indicates that an end of bad packet character
was received.
err_rr_bip8
(1)
Output
rrefclk
Indicates that a BIP-8 error was detected in
the received link management packet.
err_rr_crc
(1)
Output
rrefclk
Indicates that a CRC error was detected in the
received segment/packet.
err_rr_fcrx_bne
(1)
Output
rrefclk
Indicates that a flow control link management
packet was received, but flow control is not
enabled.
err_rr_roerx_bne
(1)
Output
rrefclk
Indicates that a retry-on-error link
management packet was received, but Retry-
on-error parameter is not enabled.
err_rr_invalid_lmprx
(1)
Output
rrefclk
Indicates that an invalid link management
packet was received.
err_rr_missing_start_dcw
(1)
Output
rrefclk
Indicates that data byte(s) received, but a
start of data control word (DCW) is missing.
err_addr_mismatch
(1)
Output
rrefclk
Indicates that the start and end address fields
do not match. Segments are marked with an
error. Possible packets are destined for an
invalid address.
err_rr_pol_rev_required
(1)
Output
rrefclk
May indicate catastrophic error. Polarity on
the input ALTGXB lines is reversed; the
MegaCore function cannot operate.
If you see the signal for the first time, you
should manually reset the core. If the signal
triggers again after you reset, then it
confirms a catastrophic error.
err_rr_dskfifo_oflw
(1)
Output
rrefclk
Indicates that deskew FIFO buffer has
overflowed. Link restarts.
stat_rr_dskw_done_bc
(1)
Output
rrefclk
Indicates that a bad column was received
after successful deskew completion. Link is
restarted.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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