Altera SerialLite II IP Core Uživatelský manuál Strana 81
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- Tabulka s obsahem
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Hodnocené. / 5. Na základě hodnocení zákazníků
Chapter 4: Functional Description 4–27
Signals
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Table 4–8 shows the Atlantic interface signals for streaming mode.
Table 4–9 shows the protocol processor’s error, status, and control signals.
txhpp_err
Input
txhpp_clk
Error indicator on the Atlantic interface.
txhpp_mty[
tm
-1:0]
(4)
Input
txhpp_clk
Number of empty bytes in the data word.
txhpp_dat[
td
-1:0]
(5)
Input
txhpp_clk
User data bits.
txhpp_adr[3:0]
Input
txhpp_clk
User-defined packet ID.
Notes to Table 4–7:
(1) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example,
err_rr_crc0
is the CRC error
signal from SerialLite II receiver block 0.
(2) m is the empty value, which is log2 (data width).
(3) d is the data width, which is 8 × transfer size × the RX number of lanes.
(4) tm is the empty value, which is log2 (data width).
(5) td is the data width, which is 8 × transfer size × the TX number of lanes.
Table 4–7. Atlantic Interface Signals (Part 3 of 3)
Signal Direction Clock Domain Description
Table 4–8. Atlantic Interface Signals for Streaming Mode
Signal Direction Clock Domain Description
rxrdp_dat [d-1:0]
(1)
,
(2)
Output
rrefclk
Received user data bits.
rxrdp_ena
(1)
Output
rrefclk
Enable signal on the Atlantic interface.
Indicates that the data is valid on the current clock
cycle.
txrdp_dat [td-1:0]
(3)
Input
tx_coreclock
User data bits to be transmitted.
txrdp_ena
Input
tx_coreclock
Enable signal on the Atlantic interface.
Indicates that the data is valid.
txrdp_dav
Output
tx_coreclock
Indicates that the core is requesting the user data to
stop while the core inserts the clock compensation
sequence.
If Clock Compensation is not enabled, this signal will
always be high while the link is up.
Notes to Table 4–8:
(1) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example,
err_rr_crc0
is the CRC error
signal from SerialLite II receiver block 0.
(2) n is = FIFO SIZE / (
TSIZE * RX
Number of Lanes).
(3) tn is = FIFO SIZE / (
TSIZE * TX
Number of Lanes).
Table 4–9. Protocol Processor’s Error, Status and Control Signals (Part 1 of 2)
Signal Direction Clock Domain Description
err_rr_rxrdp_oflw
Output
rrefclk
Indicates that the Atlantic FIFO buffer has overflowed
and data has been lost when Clock Compensation is
disabled (regular data port).
err_rr_rxhpp_oflw
Output
rrefclk
Indicates that the Atlantic FIFO buffer has overflowed
and data has been lost when Clock Compensation is
disabled (priority data port).
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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