Altera SerialLite II IP Core Uživatelský manuál Strana 105
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Chapter 5: Testbench 5–19
Example Testbench – Verilog HDL
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
begin
/////////////////////////////////////////////
/
// Generate RDP packets for SISTER
/////////////////////////////////////////////
/
@(posedge trefclk);
agen_dat_sis.verbose(1);
agen_dat_sis.ipg(0,5);
amon_dat_dut.verbose(1);
fork
while ( pkt_cnt_dat_sis > 0 ) begin :
send_loop_dat_sis
integer size;
integer err;
reg [7:0] addr;
addr = $dist_uniform(seed,0,255);
size = $dist_uniform(seed,1,1024);
err = $dist_uniform(seed,0,1);
agen_dat_sis.send_packet(addr,size,err);
reset_watchdog_timer;
pkt_cnt_dat_sis = pkt_cnt_dat_sis - 1;
end
begin
amon_dat_dut.wait_all_packets(packets_to_send
);
end
join
end
Send regular data packets (on Atlantic interface) to the
SISTER MegaCore function.
AGEN and AMON instantiations are set to display verbose
messages.
Set AGEN to insert random inner packet gaps.
Launch two processes in parallel:
- Send regular data packets to the SISTER.
Define packet size, error, address.
Packet address is a random number from 0 to 255.
Packet size is a random number from 1 to 1,024.
Packet err is a random number from 0 to 1.
Call the AGEN send packet task (regular data, SISTER).
Reset watchdog with every packet being sent.
Repeat this loop pkt_cnt_dat_sis times.
- Wait for the other side (Atlantic interface of the DUT) to
receive all these packets.
Table 5–12. Example of a Demonstration Testbench (Part 3 of 5)
Main Section Comments
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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