Altera SDI II MegaCore Uživatelský manuál Strana 83
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Signal Width Direction Description
tx_rst
1 Input Reset signal for the transmitter. This signal is active high and
level sensitive. This reset signal must be synchronous to tx_
coreclk clock domain.
tx_pclk
1 Input Parallel clock input signal for the transmitter. Driven by the tx_
clkout signal.
• SD-SDI = 148.5 MHz
• HD-SDI = 74.25 MHz or 74.175 MHz
• 3G-SDI = 148.5 MHz or 148.35 MHz
• HD-SDI Dual Link = 74.25 MHz or 74.175 MHz
• Dual Standard = 148.5 MHz or 148.35 MHz
• Triple Standard = 148.5 MHz or 148.35 MHz
tx_datain
20 Input User-supplied parallel data signal for the transmitter.
• SD-SDI = bits 19:10 unused; bits 9:0 C, Y, C, Y multiplex
• HD-SDI = bits 19:10 Y; bits 9:0 C
• HD-SDI dual link = bits 19:10 Y link A, bits 9:0 C link A
• 3G-SDI Level A = bits 19:10 Y; bits 9:0 C
• 3G-SDI Level B = bits 19:10 C, Y multiplex (link A); bits 9:0
C, Y multiplex (link B)
• Dual Standard = bits 19:10 Y; bits 9:0 C
• Triple Standard = bits 19:10 Y; bits 9:0 C.
Note: Not applicable for Arria 10 devices.
tx_datain_valid
1 Input Parallel data valid signal for the transmitter. The timing (H:
High, L: Low) must be synchronous to tx_pclk clock domain
and have the following settings:
• SD-SDI = 1H 4L 1H 5L
• HD-SDI = H
• 3G-SDI = H
• HD-SDI Dual Link = H
• Dual standard = SD (1H 4L 1H 5L); HD (1H 1L)
• Triple standard = SD (1H 4L 1H 5L); HD (1H 1L); 3G (H)
Otherwise, this signal can be driven by tx_dataout_valid for
SD-SDI, dual standard, and triple standard.
Note:
Not applicable for Arria 10 devices.
rx_rst_proto_out
1 Output Reset the receiver protocol downstream logic. This generated
signal is synchronous to rx_clkout clock domain and must be
used to drive the rx_rst_proto_in signal of the receiver
protocol block.
UG-01125
2015.05.04
SDI II IP Core Signals
4-41
SDI II IP Core Functional Description
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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