Altera SDI II MegaCore Uživatelský manuál Strana 26
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- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
This design generates two transceiver PHY reset controllers—one for TX and one for RX. These reset
controllers are connected to the transceiver to control the reset sequence. The PHY adapter controls the
rx_manual and rx_is_lockedtodata input signals of the reset controller. If you want to bypass the PHY
adapter, you must copy the assignment of these input signals in the sdi_ii_phy_adapter.v file to your design.
The table below describes how you should connect the input signals.
Table 3-4: Connecting Input Signals
Input Signal Connection
rx_manual Connect this signal to the rx_ready port of the PHY reset controller to
avoid any disturbance from short interference after the receiver is
locked.
rx_is_lockedtodata Connect this signal to an output from a multiplexer between rx_is_
lockedtoref and rx_is_lockedtodata ports from the transceiver,
with the rx_set_locktoref acting as the selector. The receiver operates
in locktoref mode when it receives SD video data. rx_is_lockedto-
data is not stable in this mode.
Note: The Transceiver Reconfiguration Controller that was used in the design examples for Arria V,
Cyclone V, and Stratix V devices are not applicable for Arria 10 devices. The reconfiguration
interface is now integrated into the transceiver. Each transceiver should pair with a reconfiguration
controller if it requires reconfiguration.
Design Examples for Arria V, Cyclone V, and Stratix V Devices
Figure below illustrates the generated design example entity and simulation testbench for Arria V,
Cyclone V, and Stratix V devices. This design example consists of a video pattern generator, transceiver
reconfiguration controller, reconfiguration management, loopback path, and various SDI blocks
occupying two transceiver channels.
UG-01125
2015.05.04
Design Examples for Arria V, Cyclone V, and Stratix V Devices
3-11
SDI II IP Core Getting Started
Altera Corporation
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- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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