Altera SDI II MegaCore Uživatelský manuál Strana 3
- Strana / 89
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
TX Sample.......................................................................................................................................4-18
Clock Enable Generator................................................................................................................4-18
RX Sample.......................................................................................................................................4-19
Detect Video Standard..................................................................................................................4-21
Detect 1 and 1/1.001 Rates............................................................................................................4-21
Transceiver Controller..................................................................................................................4-21
Descrambler....................................................................................................................................4-22
TRS Aligner.....................................................................................................................................4-23
3Gb Demux.....................................................................................................................................4-24
Extract Line.....................................................................................................................................4-24
Extract Payload ID.........................................................................................................................4-24
Detect Format.................................................................................................................................4-24
Sync Streams...................................................................................................................................4-25
Convert SD Bits..............................................................................................................................4-26
Insert Sync Bits...............................................................................................................................4-26
Clocking Scheme........................................................................................................................................4-27
SDI II IP Core Signals................................................................................................................................4-27
Additional Information......................................................................................A-1
Document Revision History......................................................................................................................A-1
TOC-3
Altera Corporation
- SDI II IP Core User Guide 1
- Contents 2
- Altera Corporation 3
- Item Description 4
- SDI II IP Core Overview 6
- SMPTE372 Dual Link Support 7
- HD Dual-Link Receiver 9
- 3-GB Receiver 10
- SMPTE RP168 Switching Support 11
- Dynamic TX Clock Switching 12
- UG-01125 13
- 2015.05.04 13
- Resource Utilization 14
- Block Memory Bits 15
- Registers 15
- Secondary Logic 15
- Installation and Licensing 16
- Design Walkthrough 16
- Launching IP Catalog 17
- Parameterizing the IP Core 18
- Timing Violation 19
- Programming an FPGA Device 20
- Design Reference 20
- SDI II IP Core Parameters 21
- Parameter Value Description 22
- Design Examples 24
- Testbench 25
- Example Design 25
- Input Signal Connection 26
- Design Example 27
- Video Pattern Generator 30
- Send Feedback 30
- Related Information 31
- Interfaces 36
- Logical Channel Number 36
- Signal Width Directio 42
- Description 42
- Protocol 44
- TX PHY Management 45
- & PHY Adapter 45
- TX Protocol Transceiver 45
- Payload ID 45
- Transceiver 47
- Receiver 48
- RX Protocol 49
- RX PHY Management 49
- Management 50
- & PHY Adapter Transceiver 50
- PHY Adapter 52
- Submodules 56
- Insert/Check CRC 57
- Insert Payload ID 57
- Match TRS 59
- Scrambler 59
- TX Sample 60
- Clock Enable Generator 60
- RX Sample 61
- Step Process Description 62
- Detect Video Standard 63
- Detect 1 and 1/1.001 Rates 63
- Transceiver Controller 63
- Descrambler 64
- TRS Aligner 65
- OUTPUT DATA 66
- OUTPUT LN 66
- Sync Streams 67
- Convert SD Bits 68
- Insert Sync Bits 68
- Clocking Scheme 69
- SDI II IP Core Signals 69
- Additional Information 87
- Date Version Changes 88
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