Altera Phase-Locked Loop Uživatelský manuál Strana 1

Altera Phase-Locked Loop (Altera PLL) IP Core UserGuide2015.05.04UG-01087SubscribeSend FeedbackThe Altera PLL megafunction IP core allows you to confi

The actual frequency is the closest frequency setting (best approximate of the requested settings) that canbe implemented in the PLL circuit.The outpu

Table 7: adjpllin Cascading for Supported DevicesDevice adjpllin Cascading (Upstream PLL — Downstream PLL)• Arria V GX B5 and B7• Arria V GT D7• FRACT

Device adjpllin Cascading (Upstream PLL — Downstream PLL)• Stratix V E E9 and EB• Stratix V GX A9, AB, B9, and BB• FRACTIONALPLL_X0_Y38 — FRACTIONALPL

Figure 2: PLL cclk Cascading and adjpllin Cascading Modesadjpllin Cascadingcclk CascadingOutput Counter 17Upstream PLLcclk Portadjpllin PortDownstream

Sources Descriptionrefclkin[1] Clock source from adjacent PMA triplet LVPECL buffer.clkin[0] Dedicated clock input for fractional PLL from regular I/O

Figure 3: PLL Output Counter Cascading ModeUpstream CounterDownstream CounterPLL Output CounterCascade ChainUG-010872015.05.04PLL Output Counter Casca

PortsTable 9: Altera PLL PortsPort Name Type Condition Descriptionfbclk Input OptionalThe external feedback input port for the PLL.The Altera PLL IP c

Port Name Type Condition Descriptionextswitch Input Required Assert this input signal high (1’b1) to manuallyswitch the clock for at least 3 cycles.ac

Date Version ChangesMarch 2013 1.2• Added the “Reference Clock Switchover” section.• Added the “PLL to PLL Cascading” section.• Added new parameters f

Altera PLL IP Core Parameters - General TabTable 1: Altera PLL IP Core Parameters - General TabParameter Legal Value DescriptionDevice Speed Grade Str

Parameter Legal Value DescriptionOperation Mode direct,externalfeedback,normal,sourcesynchronous,zero delaybuffer, or lvdsSpecifies the operation of t

Parameter Legal Value DescriptionDesired Frequency (1)— Specifies the output clock frequency of the correspondingoutput clock port, outclk[], in MHz.

Parameter Legal Value DescriptionSecond Reference ClockFrequency—Selects the frequency of the second input clock signal. Thedefault value is 100.0 MHz

Altera PLL IP Core Parameters - Cascading TabTable 3: Altera PLL IP Core Parameters - Cascading TabParameter Legal Value DescriptionCreate a ‘cascade

Parameter Legal Value DescriptionNumber of Dynamic PhaseShifts— Selects the number of phase shift increments. The size of asingle phase shift incremen

(lock) on the frequency of the input or reference signal. The synchronization or negative feedback loop ofthe system forces the PLL to be phase-locked

PLL LockThe PLL lock is dependent on the two input signals in the phase frequency detector. The lock signal is anasynchronous output of the PLLs.The n