Altera Embedded Peripherals IP Uživatelský manuál Strana 165
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Hodnocené. / 5. Na základě hodnocení zákazníků
Bit(s) Name Description
5 UNDERFLOW Is set to 1 for 1 cycle every time the FIFO underflows. The FIFO
underflows when an Avalon read master reads from an empty FIFO.
UNDERFLOW is only valid when Allow backpressure is off.
These fields are identical to those in the status register and are set at the same time; however, these fields
are only cleared when software writes a one to clear (W1C). The event fields can be used to determine if a
particular event has occurred.
Table 16-6: Event Bit Field Descriptions
Bit(s) Name Description
1 E_FULL Has a value of 1 if the FIFO has been full and the bit has not been
cleared by software.
0 E_EMPTY Has a value of 1 if the FIFO has been empty and the bit has not been
cleared by software.
3 E_ALMOSTFULL Has a value of 1 if the fill level of the FIFO has been greater than the
almostfull threshold value and the bit has not been cleared by
software.
2 E_ALMOSTEMPTY Has a value of 1 if the fill level of the FIFO has been less than the
almostempty value and the bit has not been cleared by software.
4 E_OVERFLOW Has a value of 1 if the FIFO has overflowed and the bit has not been
cleared by software.
5 E_UNDERFLOW Has a value of 1 if the FIFO has underflowed and the bit has not been
cleared by software.
The table below provides a mask for the six STATUS fields. When a bit in the event register transitions
from a zero to a one, and the corresponding bit in the interruptenable register is set, the master is
interrupted.
Table 16-7: InterruptEnable Bit Field Descriptions
Bit(s) Name Description
1 IE_FULL Enables an interrupt if the FIFO is currently full.
0 IE_EMPTY Enables an interrupt if the FIFO is currently empty.
3 IE_ALMOSTFULL Enables an interrupt if the fill level of the FIFO is greater than the
value of the almostfull register.
2 IE_ALMOSTEMPTY Enables an interrupt if the fill level of the FIFO is less than the value of
the almostempty register.
4 IE_OVERFLOW Enables an interrupt if the FIFO overflows. The FIFO overflows when
an Avalon write master writes to a full FIFO.
5 IE_UNDERFLOW Enables an interrupt if the FIFO underflows. The FIFO underflows
when an Avalon read master reads from an empty FIFO.
6 ALL Enables all 6 status conditions to interrupt.
16-10
Software Control
UG-01085
2014.24.07
Altera Corporation
On-Chip FIFO Memory Core
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 10
- Introduction 14
- Device Support 15
- December 16
- Initial release. — 16
- SDRAM Controller Core 17
- Avalon-MM Interface 18
- Off-Chip SDRAM Interface 18
- Memory Profile Page 21
- Timing Page 22
- SDRAM Memory Model 23
- Symptoms of an Untuned PLL 26
- Example Calculation 27
- Parameter Symbol 28
- Value (ns) in -7 Speed Grade 28
- Min. Max 28
- Parameter Symbol Value (ns) 28
- Tri-State SDRAM 31
- Configuration Parameter 32
- Interface 33
- Reset and Clock Requirements 38
- Architecture 38
- Block Level Usage Model 39
- Compact Flash Core 41
- Required Connections 42
- (32-bit Word Address) 54
- Register Name R/W 54
- Bit Description 54
- JTAG UART Core 58
- Read and Write FIFOs 59
- JTAG Interface 59
- Host-Target Connection 59
- Simulation Settings 61
- UART Core 70
- RS-232 Interface 71
- Transmitter Logic 71
- Instantiating the Core 72
- Data Bits, Stop Bits, Parity 73
- Synchronizer Stages 74
- Flow Control 74
- Streaming Data (DMA) Control 74
- Request Description 79
- Bit Name Access Description 81
- May 2008 86
- 16550 UART 87
- Unsupported Features 88
- General Architecture 90
- Configuration Parameters 90
- DMA Support 91
- FPGA Resource Usage 91
- Timing and Fmax 92
- Avalon-MM Slave 93
- Overrun/Underrun Conditions 94
- Hardware Auto Flow-Control 95
- 16550 UART API 98
- Private APIs 99
- UART Device Structure 100
- Figure 9-7: 101
- Driver Examples 102
- UG-01085 103
- 2014.24.07 103
- Document Revision History 106
- SPI Core 107
- txdata 108
- Receiver Logic 109
- Master and Slave Modes 109
- Slave Mode Operation 110
- Multi-Slave Environments 110
- Configuration 111
- Data Register Settings 112
- Timing Settings 112
- Software Programming Model 113
- Software Files 114
- Register Map 115
- # Name Description 116
- Date and 118
- Document 118
- Core Overview 119
- Functional Description 119
- Interrupt Behavior 121
- PIO Core 123
- Data Input and Output 124
- Edge Capture 124
- IRQ Generation 124
- Example Configurations 125
- Input Options 126
- Operation 132
- PCI Lite Core 135
- Avalon-MM Ports 137
- Prefetchable Avalon-MM Master 137
- I/O Avalon-MM Master 138
- PCI Bus Access Slave 138
- Master and Target Performance 139
- Space Indicator 141
- (Bits 1:0) 141
- Description 141
- Avalon-to-PCI Write Request 142
- Ordering of Requests 143
- Send Feedback 145
- PCI Timing Constraint Files 146
- Simulation Considerations 147
- Simulation Flow 149
- MDIO Core 151
- MDIO Frame Format (Clause 45) 152
- MDIO Clock Generation 153
- Interfaces 153
- Parameter 154
- Configuration Registers 154
- On-Chip FIFO Memory Core 156
- Offset Bits Field Description 158
- FIFO Settings 161
- Interface Parameters 161
- Software Control 163
- Field Type Description 164
- Bit(s) Name Description 164
- Software Example 166
- On-Chip FIFO Memory API 167
- Multi-Channel Shared FIFO 176
- Parameters 177
- Address Width 178
- Name Access Reset 180
- Bytes Converter Cores 185
- Feature Property 186
- Transaction 190
- DMA Descriptors 197
- Error Conditions 198
- Signal Type Description 199
- Timeouts 206
- Data Structure 207
- SG-DMA API 208
- Name Description 209
- Overview 217
- Feature Description 217
- Component Interface 220
- Descriptor Slave Port 221
- Component GUI 222
- Byte Lanes 223
- Read and Write Address Fields 224
- Length Field 224
- Sequence Number Field 225
- Read and Write Stride Fields 225
- Control Field 225
- Bit Sub-Field Name Definition 226
- Register Map of mSGDMA 228
- Status Register 229
- Control Register 229
- Bit Name Description 230
- Offset Access 3 2 1 0 230
- Unsupported Feature 231
- DMA Controller Core 232
- Setting Up DMA Transactions 233
- Advanced Options 235
- Video Sync Generator 242
- Parameter Name Description 244
- Horizontal sync pulse 245
- Horizontal front porch 245
- Horizontal blank pixels 245
- Pixel Converter 246
- Interval Timer Core 249
- Counter Size 251
- Hardware Options 251
- Bit Name R/W/C Description 255
- Mutex Core 258
- Mutex API 260
- Mailbox Core 264
- Mailbox API 267
- Functional Blocks 273
- Register Maps 275
- Run-time Initialization 285
- Board Support Package 285
- VIC IRQ RRS RIL 291
- November 293
- Altera FPGA 294
- Core Behavior 295
- System ID Core 298
- Performance Counter Core 301
- Global Counter 302
- Using the Performance Counter 304
- Name (1) Meaning 305
- Performance Counter API 306
- PERF_START_MEASURING() 307
- PERF_STOP_MEASURING() 307
- PERF_BEGIN() 307
- PERF_END() 308
- PLL Cores 312
- Registers 313
- PLL Core 313
- ALTPLL Megafunction 313
- Instantiating the PLL Core 314
- Altera MSI to GIC Generator 320
- Interrupt Servicing Process 321
- Registers of Component 322
- Altera SMBus Core Interface 324
- Component Parameterization 326
- Frequency Register 331
- 32-bit Counter 332
- Software Access 334
- Implementation Details 335
- IP Caveats 336
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