Altera DDR SDRAM Controller Uživatelský manuál Strana 67
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Hodnocené. / 5. Na základě hodnocení zákazníků
Chapter 3: Functional Description 3–31
Parameters
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
Parameters
The parameters can be set only in IP Toolbench (refer to “DDR & DDR2 SDRAM
Controller Walkthrough” on page 2–9). Table 3–10 shows the global parameters.
clk_to_sdram Output Clock for the memory device.
clk_to_sdram_n Output Inverted clock for the memory device.
ddr_a[] Output Memory address bus.
ddr_ba[] Output Memory bank address bus.
ddr_cas_n Output Memory column address strobe signal.
ddr_cke[] Output Memory clock enable signals.
ddr_cs_n[] Output Memory chip select signals.
ddr_dm[] Output Memory data mask signal, which masks individual bytes during writes.
ddr_odt Output Memory on-die termination control signal (DDR2 SDRAM only).
ddr_ras_n Output Memory row address strobe signal.
ddr_we_n Output Memory write enable signal.
Note to Table 3–9:
(1) You can change the ddr_ signal name prefix in IP Toolbench.
Table 3–9. DDR & DDR2 SDRAM Interface Signals (Part 2 of 2) (Note 1)
Signal Name Direction Description
Table 3–10. Global Parameters
Parameter Value Units Description
Presets Part
number or
custom
— A part number for a particular memory device, module, or the name of an
Altera development board. Choosing an entry other than Custom sets many of
the parameters in the wizard to the correct value for the specified part. If any
such parameter is changed to a value that is not supported by the specified
device, the preset automatically changes to custom. You can add your own
devices or boards to this list by editing the memory_types.dat file in the
\constraints directory.
Clock speed > 75 (1) MHz The clock frequency used by the memory controller. Because the controller
uses double data rate, the data rate is twice the clock frequency.
Note to Table 3–10:
(1) Depends on the FPGA and the memory device that you choose.
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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