Altera DDR SDRAM Controller Uživatelský manuál Strana 59
- Strana / 106
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Chapter 3: Functional Description 3–23
Interfaces & Signals
© March 2009 Altera Corporation DDR and DDR2 SDRAM Controller Compiler User Guide
4. The controller returns the read data for the first request by asserting the
local_rdata_valid signal. The exact number of clock cycles between the
controller accepting the request and returning the data depends on the number of
other requests pending in the controller, the state the memory is in, and the timing
requirements of the memory (e.g., the CAS latency).
5. The controller returns the read data for the subsequent read requests.
Read-Write-Read-Write
Figure 3–15 on page 3–23 shows a sequence of interleaved reads and writes.
1. The user logic requests a read request by asserting the local_read_req signal
along with the size and address for that read. Because the local_ready signal is
high, that request can be considered accepted.
Figure 3–15. Read-Write-Read-Write
Notes to Figure 3–15:
(1) The local_cs_addr, local_row_addr, local_bank_addr, and local_col_addr signals are a representation of the
local_addr signal.
(2) DDR Command shows the command that the command signals are issuing.
clk
local_read_req
local_write_req
local_ready
local_size
local_cs_addr (
1
)
local_row_addr (
1
)
local_bank_addr (
1
)
local_col_addr (
1
)
local_rdvalid_in_n
local_rdata_valid
local_rdata
local_wdata_req
local_wdata
ddr_cs_n
ddr_cke
ddr_a
ddr_ba
DDR Command (
2
)
ddr_ras_n
ddr_cas_n
ddr_we_n
ddr_dm
ddr_dq
ddr_dqs
0 01
0
2 0 2 02
0000
0143 0021 0143 00000021
0
1 2 1 02
000
019 086 01A 000085
FFD0 9A38
DF08 D5CD 14D9D5CD
FF
FB FF FB FE FF FE FF FB FF FE FFFE
FF
0000
0143 0000 0032 0021 0000 010C0000 0034 0000 010A 0000010A
0
1 0 1 2 0 2 0 1 0 2 02
NOP
ACT NOP RD ACT NOP WR NOP RD NOP WR NOPWR
DDR SDRAM
Interface
Local Interface
[1] [2] [3] [4] [6][5]
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Software Version: 9.0 1
- Document Date: March 2009 1
- UG-DDRSDRAM-10.0 2
- Contents 3
- 1. About This Compiler 5
- Features 6
- General Description 6
- Note to Figure 1–1: 7
- Note to Table 1–3: 8
- Installation and Licensing 9
- OpenCore Plus Evaluation 10
- 2. Getting Started 11
- SOPC Builder Design Flow 12
- Parameterize 14
- Constraints 15
- Add/Update Component 15
- Create Your Top-Level Design 16
- Edit the PLL 17
- Program a Device 18
- Figure 2–1. System Naming 24
- Set Up Simulation 25
- Generate 25
- Simulate the Example Design 27
- Notes to Table 2–2: 29
- Notes to Table 2–3: 30
- Notes to Table 2–4: 31
- Compile the Example Design 32
- Implement Your Design 34
- Set Up Licensing 35
- Control Logic 37
- Datapath 38
- Device-Level Description 41
- Figure 3–3. Datapath Timing 42
- Designing Your Own Controller 43
- DQS Group Block Diagrams 44
- Notes to Figure 3–4: 45
- Notes to Figure 3–5: 46
- Notes to Figure 3–6: 47
- Notes to Figure 3–7: 48
- PLL Configurations 49
- Stratix II Device 50
- Stratix Device 51
- Cyclone II Device 51
- Cyclone Device 51
- DLL Configurations 52
- Example Design 52
- Notes to Table 3–5: 53
- Interface Description 55
- Figure 3–13. Writes 56
- Interfaces & Signals 57
- DDR SDRAM 58
- Interface 58
- Local Interface 58
- [1] [3][2] [5][4] 58
- [1] [2] [3] [4] [6][5] 59
- User Refresh Control 60
- 200 clock cycles 63
- Note to Table 3–7: 65
- Parameters 67
- Controller 69
- Note to Table 3–15: 71
- Controller Timings 73
- Memory Timings 74
- Board Timings 75
- Project Settings 76
- Manual Timings 77
- Simulation Testing 77
- Hardware Testing 77
- (MT46V8M16-75Z) 78
- A. Manual Timing Settings 79
- Resynchronization 82
- Resynchronization Registers 83
- Notes to Figure A–2: 84
- Notes to Figure A–3: 85
- Notes to Figure A–4: 86
- Notes to Table A–5: 87
- Note to Figure A–5: 87
- DQS Postamble 88
- Postamble Logic 89
- System Clock 90
- Postamble 90
- Examples 91
- Board, Cyclone II Edition 95
- D. Maximizing Performance 101
- Adjust the PLL Phases 102
- Assign Pins 102
- Place the Fedback PLL 102
- Update the PLL Phases 103
- Additional Information 105
- Typographic Conventions 106
- Preliminary 106
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