Altera FIR Compiler II MegaCore Function Uživatelský manuál

FIR II IP CoreUser GuideSubscribeSend FeedbackUG-010722014.12.15101 Innovation DriveSan Jose, CA 95134www.altera.com

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary8 2 FractionalRateWrite 2,301 16 0 —

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary1 — Decimation — 219 3 0 — 159 23 289

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary1 supersample— Single rate Write 369

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary8 2 Interpolation Multiplebanks;Write

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary1 HalfBand— Decimation — 226 3 — 0 20

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary1 — Single rate Multiplebanks250 10 —

FIR II IP Core Getting Started22014.12.15UG-01072SubscribeSend Feedback1.Installing and Licensing IP CoresThe Altera IP Library provides many useful I

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate

Use the following features to help you quickly locate and select an IP core:• Filter IP Catalog to Show IP for active device family or Show IP for all

1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize.The parameter editor appears.2. Specify a t

ContentsAbout the FIR II IP Core...1-1Altera DSP IP Core Features...

Figure 2-3: IP Parameter EditorView IP portand parameter detailsApply preset parameters forspecific applicationsSpecify your IP variation nameand targ

Figure 2-4: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Figure 2-5: Simulation in Quartus II Design FlowPost-fit timing simulation netlist Post-fit timing simulation (3)Post-fit functional simulation net

Related InformationUsing MegaCore Functions chapter in the DSP Builder Handbook.2-10DSP Builder Design FlowUG-010722014.12.15Altera CorporationFIR II

FIR II IP Core Parameters32014.12.15UG-01072SubscribeSend FeedbackYou define a FIR filter by its coefficients. You specify the filter settings and coe

Parameter Value DescriptionClock Frequency(MHz)1–500 Specifies the frequency of the input clock.Clock Slack Integer Enables you to control the amount

Parameter Value DescriptionBack PressureSupport— Turn on this option to enable backpressuresupport. When this option is turned on, the sinksignals the

The FIR II IP core supports scaling on the coefficient set.1. Click Import coefficients, in the File name box, specify the name of the .txt file conta

Channel Input and Output Format...4-15FIR II IP Core Multipl

Parameter Value DescriptionOutput Data Type Signed BinarySigned FractionalBinarySpecifies whether the output data is in a signedbinary or a signed fra

MSB and LSB Truncation, Saturation, and RoundingThe output options on the parameter editor allow you to truncate or saturate the MSB and to truncate o

Parameter Value DescriptionDevice Family Menu of supporteddevicesSpecifies the target device family.Speed grade Fast, medium, slow Specifies the speed

example, the threshold that determines whether to use M9K blocks rather than MLAB blocks onStratix IV devices.1. Set the default threshold value, to

FIR II IP Core Functional Description42014.12.15UG-01072SubscribeSend FeedbackThe FIR II IP core generates the Avalon-ST register transfer level (RTL)

higher clock rate by driving the ast_source_ready signal of the FIR II IP core high, and not connectingthe ast_sink_ready signal.The sink and source i

Single Channel on Single WireFigure 4-2: Single Channel on Single Wire Sink to FIR II IP CoreWhen transferring a single channel of 8bit dataFIR Filter

Multiple Channels on Single WireFigure 4-3: Multiple Channels on Single Wire Sink to FIR II IP coreWhen transferring a packet of data over multiple ch

Figure 4-4: Multiple Channels on Multiple WiresThe sink interface to the FIR II IP core when transferring a packet of data over multiple channels onmu

Figure 4-5: Timing Diagram of Multiple Channels on Multiple WiresThe sink interface to the FIR II IP core when transferring a packet of data over mult

About the FIR II IP Core12014.12.15UG-01072SubscribeSend FeedbackThe Altera® FIR II IP core provides a fully-integrated finite impulse response (FIR)

Figure 4-6: Multiple Channels on Multiple WiresThe FIR II IP core to the source interface when transferring a packet of data over multiple channels on

Figure 4-7: Timing Diagram of Multiple Channels on Multiple WiresThe FIR II IP core to the source interface when transferring a packet of data over mu

Signal Direction Width Descriptionast_sink_data Input (Data width +Bank width) ×the number ofchannel inputwires(PhysChanIn)where,Bank width=Log2(Numbe

Signal Direction Width Descriptionast_sink_error Input 2 Error signal indicating Avalon-ST protocolviolations on the sink side:• 00: No error• 01: Mis

Signal Direction Width Descriptioncoeff_in_address Input Number ofcoefficientsAddress input to write new coefficient data.coeff_in_we Input 1 Write en

To achieve TDM, the IP core requires a serializer and deserializer before and after the reused hardwareblock to control the timing. The ratio of syste

into the fewest number of wires (vector width) that will support that rate. For example, an interpolate bytwo FIR II IP core filters might have two wi

Figure 4-10: Channelization for Four Channels with a TDM Factor of 3A TDM factor of 3 combines four input channels into two wires (inputChannelNum = 4

Figure 4-13: Four Channels on Four Wiresvalidchanneldata0data0data1data1c0(0) c0(1) c0(2) c0(3) c0(4)c0(5)c0(6) c0(7)0c1(0) c1(1) c1(2) c1(3) c1(4)c1(

Figure 4-17: Four Channels on Four Wires (Output)clkxOut_vxOut_0xOut_1xOut_2C0C1C2xOut_3C3This result appears to be vertical, but that is because the

• Avalon® Streaming (Avalon-ST) interfaces• DSP Builder ready• Testbenches to verify the IP core• IP functional simulation models for use in Altera-su

Figure 4-20: Correct Input Format (15 valid cycles, 17 invalid cycles)aresetclkxin_v[0]xin_c[7:0]xin_0[7:0]xout_v[0]xout_c[7:0]xout_0[17:0]xout_1[17:0

Figure 4-23: Correct Input Format (11 valid cycles, 9 invalid cycles)aresetclkxin_v[0]xin_c[7:0]xin_0[7:0]xin_1[7:0]xout_v[0]xout_c[7:0]xout_0[17:0]xo

Figure 4-25: Correct Input Format (11 valid cycles, 11 invalid cycles)clkaresetxin_v[0]xin_c[7:0]xin_0[7:0]xin_1[7:0]xout_v[0]xout_c[7:0]xout_0[17:0]x

Figure 4-27: Super Sample Rate Filter (clkRate=100, inputRate=200) with inChans=2IfinputChannelNum = 2clkxln_vxln_0xln_1xOut_vxOut_cxOut_0xOut_1xOut_2

Figure 4-28: Timing Diagram of a Single-Channel Filter with 4 Coefficient Banksclkast_sink_validast_sink_data[9:0]bankin_0[1:0]xin_0[7:0]xout_v[0]xout

the coefficient with new data. The new coefficient data is read out after coefficient reloading to verifywhether the coefficient reloading process is

Figure 4-31: Timing Diagram of Coefficient Reloading in Write modeIn this mode, the IP core loads one coefficient data. The new coefficient data (123)

Document Revision History52014.12.15UG-01072SubscribeSend FeedbackFIR II IP Core User Guide revision historyDate Version Changes2014.12.15 14.1• Added

Device Family SupportStratix V FinalOther device families No supportDSP IP Core VerificationBefore releasing a version of an IP core, Altera runs comp

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary8 2 Decimation Write 2,120 24 0 — 1,2

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary8 1 Interpolation — 381 5 0 — 442 32

ParametersALMDSPBlocksMemory RegistersfMAX(MHz)Channel Wires Filter Type Coefficients M10K M20K Primary Secondary1 HalfBand— Interpolation — 254 3 0 —