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sections explain how you set and use these register values to derive the extended Tx delay measurement
information.
M/N Ratio Selection
As your selected M/N ratio approaches 1, the accuracy provided by the extended delay measurement
increases.
Table 3-15: Resolution as a Function of M/N Ratio at 3.072 Gbps
M N cpri_clkout Period ex_delay_clk
Period
Resolution
128 127
13.02 ns (1/76.80 MHz)
13.12 ns ±100 ps
64 63 13.22 ns ±200 ps
1 4 3.25 ns ±3.25 ns
Example 3-3: Extended Delay Measurement Calculation Example
This section walks you through an example that shows you how to calculate the frequency at
which to run ex_delay_clk, and how to program and use the registers to determine the delay
through the CPRI Receive Buffer.
For example, assume your CPRI v6.0 IP core runs at CPRI line bit rate 3.072 Gbps. In this case,
the cpri_clkout frequency is 76.80, so a cpri_clkout cycle is 1/76.80 MHz.
If your accuracy resolution requirements are satisfied by an M/N ratio of 128/127, perform the
following steps:
1. Program the value N=127 in the rx_msrm_period field of the RX_EX_DELAY register at offset
0x54.
2. Perform the following calculation to determine the ex_delay_clk frequency that supports
your desired accuracy resolution:
ex_delay_clk period = (M/N) cpri_clkout period = (128/127)(1/(76.80 MHz)= 13.123356
ns.
Based on this calculation, the frequency of ex_delay_clk is 1/(13.123356 ns)
The following steps assume that you run ex_delay_clk at this frequency.
3. Read the value of the RX_EX_DELAY register at offset 0x54.
If the rx_ex_delay_valid field of the register is set to 1, the value in the rx_ex_delay field
has been updated, and you can use it in the following calculations. For this example, assume
the value read from the rx_ex_delay field is 0x107D, which is decimal 4221.
4. Perform the following calculation to determine the delay through the Rx buffer:
Delay through Rx buffer = (rx_ex_delay x cpri_clkout period) / N = (4221 x 13.02083 ns) / 127
= 432.7632 ns.
This delay comprises (432.7632ns / 13 .02083 ns) = 33.236 cpri_clkout clock cycles.
These numbers provide you the result for this particular example. For illustration, the preceding
calculation shows the result in nanoseconds. You can derive the result in cpri_clkout clock
cycles by dividing the preceding result by the cpri_clkout clock period. Alternatively, you can
3-42
Extended Delay Measurement
UG-01156
2014.08.18
Altera Corporation
Functional Description
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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