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Figure 3-16: Direct VS RX Timing Diagram
Direct VS RX interface behavior in a CPRI v6.0 IP core running at 0.6144 Gbps.
The aux_rx_x signal is not part of this interface and is available only if you turn on the AUX interface in
your CPRI v6.0 IP core variation. However, its presence in the timing diagram explains the timing of the
vs_rx_valid output signal that you use to identify the clock cycles with valid VS data.
The aux_rx_x[7:0] signal (labelled simply aux_rx_x) holds the eight-bit index of the basic frame in the
hyperframe, from the perspective of the AUX interface. The subchannel index is the control word index
modulo 64, available in aux_rx_x[5:0] if you turn on the AUX interface in your CPRI IP core.
cpri_clkout
79
80
81 124
125
15
16
17 60
61
0000 1000 000000001000
X (D2)XXX XX(D1)XXX
aux_rx_x
aux_rx_x[5:0]
vs_rx_valid[3:0]
vs_rx_data[31:0]
Pointer-P = 60
3-24
Direct Vendor Specific Access Interface
UG-01156
2014.08.18
Altera Corporation
Functional Description
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