Altera CPRI v6.0 MegaCore Function Uživatelský manuál Strana 2
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Contents
About the CPRI v6.0 IP Core..............................................................................1-1
CPRI v6.0 IP Core Supported Features.....................................................................................................1-2
CPRI v6.0 IP Core Device Family and Speed Grade Support................................................................1-3
Device Family Support....................................................................................................................1-3
CPRI v6.0 IP Core Performance: Device Speed Grade Support................................................1-4
IP Core Verification.....................................................................................................................................1-4
Resource Utilization for CPRI v6.0 IP Cores...........................................................................................1-4
Release Information.....................................................................................................................................1-6
Installation and Licensing Features...........................................................................................................1-6
OpenCore Plus Evaluation............................................................................................................. 1-6
OpenCore Plus Time-Out Behavior..............................................................................................1-7
Getting Started with the CPRI v6.0 IP Core.......................................................2-1
Installation and Licensing...........................................................................................................................2-2
Specifying IP Core Parameters and Options............................................................................................2-2
Files Generated for Altera IP Cores...........................................................................................................2-3
CPRI v6.0 IP Core Parameters...................................................................................................................2-7
Integrating Your IP Core in Your Design: Required External Blocks................................................2-11
Adding the Clean-Up PLL............................................................................................................2-12
Adding the External TX PLL........................................................................................................2-13
Adding the External Reset Controller.........................................................................................2-14
Adding the Transceiver Reconfiguration Controller................................................................2-15
Simulating Altera IP Cores.......................................................................................................................2-16
Understanding the Testbench..................................................................................................................2-17
Running the Testbench.............................................................................................................................2-17
Functional Description....................................................................................... 3-1
Interfaces Overview.....................................................................................................................................3-1
CPRI v6.0 IP Core Clocking Structure......................................................................................................3-3
CPRI v6.0 IP Core Reset Requirements....................................................................................................3-5
Start-Up Sequence Following Reset.......................................................................................................... 3-6
AUX Interface...............................................................................................................................................3-9
AUX Interface Signals...................................................................................................................3-10
AUX Interface Synchronization.................................................................................................. 3-17
Auxiliary Latency Cycles...............................................................................................................3-17
Direct Interface CPRI Frame Data Format................................................................................3-18
Direct IQ Interface.....................................................................................................................................3-21
Direct Vendor Specific Access Interface.................................................................................................3-23
Real-Time Vendor Specific Interface......................................................................................................3-25
Direct HDLC Serial Interface...................................................................................................................3-27
Direct L1 Control and Status Interface...................................................................................................3-29
TOC-2
CPRI v6.0 MegaCore Function User Guide
Altera Corporation
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About the CPRI v6.0 IP Core 5
- Device Family Support 7
- IP Core Verification 8
- Release Information 10
- Related Information 11
- Installation and Licensing 13
- 2014.08.18 14
- File Name Description 15
- CPRI v6.0 IP Core Parameters 18
- Parameter Range Default 20
- Parameter Description 20
- Adding the Clean-Up PLL 23
- Adding the External TX PLL 24
- Simulating Altera IP Cores 27
- Understanding the Testbench 28
- Running the Testbench 28
- Parameter Value 29
- Functional Description 31
- Information 35
- AUX Interface 39
- AUX Interface Signals 40
- AUX RX Interface Data Signals 41
- AUX TX Interface Data Signals 42
- AUX Interface Synchronization 47
- Auxiliary Latency Cycles 47
- Direct IQ Interface 51
- Direct HDLC Serial Interface 57
- RX MII Signals 62
- TX MII Signals 63
- MII Status Signals 64
- CPU Interface Signals 66
- Specifying the Control Word 67
- Auto-Rate Negotiation 70
- Extended Delay Measurement 71
- Resolution 72
- Deterministic Latency 73
- CPRI Link 75
- Interface to the External PLL 78
- Testing Features 79
- CPRI v6.0 IP Core Signals 82
- Clock Name 86
- Direction 86
- CPRI v6.0 IP Core Registers 90
- 2015.02.16 91
- INTR Register 92
- L1_STATUS Register 92
- L1_CONFIG Register 93
- BIT_RATE_CONFIG Register 94
- PROT_VER Register 95
- TX_SCR Register 96
- RX_SCR Register 96
- CM_CONFIG Register 97
- CM_STATUS Register 98
- START_UP_SEQ Register 98
- START_UP_TIMER Register 99
- FLSAR Register 100
- CTRL_INDEX Register 100
- TX_CTRL Register 101
- RX_CTRL Register 102
- RX_ERR Register 102
- LOOPBACK Register 103
- RX_BFN Register 103
- Bits Field Name Type Value on 104
- Description 104
- TX_DELAY Register 105
- RX_DELAY Register 106
- TX_EX_DELAY Register 107
- RX_EX_DELAY Register 107
- ROUND_TRIP_DELAY Register 108
- XCVR_BITSLIP Register 108
- UG-01156 110
- Subscribe 110
- Send Feedback 110
- Altera Corporation 112
- Additional Information 113
- How to Contact Altera 114
- Typographic Conventions 114
- Visual Cue Meaning 115
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