Altera Clock Control Block IP Core Uživatelský manuál stáhnout pdf (Strana 20)

3–8 Chapter 3: Functional Description

Prototypes and Component Declarations

Clock Control Block (ALTCLKCTRL) Megafunction February 2014 Altera Corporation

User Guide

Prototypes and Component Declarations

This section describes the prototypes and component declarations of the

ALTCLKCTRL megafunction.

Verilog HDL Prototype

You can locate the following Verilog HDL prototype in the Verilog Design File (.v)

altera_mf.v in the <Quartus II installation directory>\eda\synthesis directory.

module altclkctrl

#( parameter clock_type = "AUTO",

parameter intended_device_family = "unused",

parameter ena_register_mode = "falling edge",

parameter implement_in_les = "OFF",

parameter number_of_clocks = 4,

parameter use_glitch_free_switch_over_implementation = "OFF",

parameter width_clkselect = 2,

parameter lpm_type = "altclkctrl",

parameter lpm_hint = "unused")

( input wire [width_clkselect-1:0] clkselect,

input wire ena,

input wire [number_of_clocks-1:0] inclk,

output wire outclk)/* synthesis syn_black_box=1 */;

endmodule //altclkctrl

VHDL Component Declaration

The following VHDL component declaration is located in the VHDL Design File

(.vhd) altera_mf_components.vhd in the <Quartus II installation

directory>\libraries\vhdl\altera_mf directory.

component altclkctrl

generic (

clock_type:string := "AUTO";

intended_device_family:string := "unused";

ena_register_mode:string := "falling edge";

implement_in_les:string := "OFF";

number_of_clocks:natural := 4;

use_glitch_free_switch_over_implementation:string := "OFF";

width_clkselect:natural := 2;

lpm_hint:string := "UNUSED";

lpm_type:string := "altclkctrl"

);

port(

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Altera Clock Control Block IP Core Uživatelský manuál Strana 20