Altera Floating-Point Uživatelský manuál

Floating-Point IP Cores User GuideSubscribeSend FeedbackUG-010582014.12.19101 Innovation DriveSan Jose, CA 95134www.altera.com

available in the Quartus II IP Catalog. For more information about using the Qsys IP Catalog, referto Creating a System with Qsys in the Quartus II Ha

Table 13-2: ALTFP_ATAN Resource Utilization and PerformanceDevice Family Function PrecisionOutputLatencyLogic usagefMAX (MHz)AdaptiveLook-UpTables(ALU

Table 13-4: ALTFP_ATAN ParametersParameterNameType Required DescriptionWIDTH_EXP Integer Yes Specifies the precision of the exponent. The bias of thee

ALTFP_SINCOS IP Core142014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_SINCOS IP core acc

Table 14-1: ALTFP_SINCOS Resource Utilization and PerformanceDevice Family Function PrecisionOutputLatencyLogic usagefMAX (MHz)AdaptiveLook-UpTables(A

Table 14-3: ALTFP_SINCOS IP Core Output SignalsPort Name Required Descriptionresult[] Yes The trigonemetric of the data[] input port in floating-point

ALTFP_ABS IP Core152014.12.19UG-01058SubscribeSend FeedbackALTFP_ABS FeaturesThe ALTFP_ABS IP core offers the following features:• Absolute value of a

Table 15-1: ALTFP_ABS Resource Utilization and Performance for the Stratix III Device FamilyPrecisionOutputLatencyLogic usagefMAX (MHz)AdaptiveLook-Up

In this example, the latency of the multiplier is set to five clock cycles, while none is being set for theabsolute value function. Thus, the absolute

Figure 15-2: ALTFP_ABS Signalsdata[]overflow_innan_indivision_by_zero_inzero_inunderflow_inclk_enclockinstALTFP_ABSresult[]overflownanunderflowzerodiv

Table 15-4: ALTFP_ABS Output SignalsPort Name Required Descriptionresult[] Yes The absolute value result of the input data. The size of thisport corre

• Optionally select preset parameter values if provided for your IP core. Presets specify initialparameter values for specific applications.• Specify

Port Name Type Required DescriptionWIDTH_MAN Integer Yes Specifies the precision of the mantissa. If thisparameter is not specified, the default is 23

ALTFP_COMPARE IP Core162014.12.19UG-01058SubscribeSend FeedbackALTFP_COMPARE FeaturesThe ALTFP_COMPARE IP core offers the following features:• Compari

Table 16-1: ALTFP_COMPARE Resource Utilization and Performance for Stratix IV DevicesDevice Family PrecisionOutputLatencyLogic UsagefMAX (MHz)Adaptive

This table lists the inputs and corresponding outputs obtained from the simulation in the waveform.Table 16-2: Summary of Input Values and Correspondi

Table 16-3: ALTFP_COMPARE Input SignalsPort Name Required Descriptionaclr No Asynchronous clear. The source is asynchronously reset when assertedhigh.

Table 16-5: ALTFP_COMPARE ParametersPort Name Type Required DescriptionWIDTH_EXP Integer Yes Specifies the precision of the exponent. If thisparameter

ALTFP_CONVERT IP Core172014.12.19UG-01058SubscribeSend FeedbackALTFP_CONVERT FeaturesThe ALTFP_CONVERT IP core offers the following features:• Convers

Table 17-2: ALTFP_CONVERT Conversion OperationsOperation FeaturesInteger-to-Float Conversion• Converts integers to the IEEE-754 standard floating-poin

Table 17-3: Latency Options for Each OperationOperation Conversion From Latency (in clock cycles)Integer-to-Float N/A 6Float-to-Integer N/A 6Float-to-

Operation Format PipelineLogic UsagefMAX (MHz)AdaptiveLook-UpTables(ALUTs)DedicatedLogicRegisters(DLRs)AdaptiveLogicModules(ALMs)Float-to-IntegerSingl

Figure 1-5: IP Core Generated Files<your_testbench>_tb.csv<your_testbench>_tb.spd<your_ip>.cmp - VHDL component declaration file<

Operation Format PipelineLogic UsagefMAX (MHz)AdaptiveLook-UpTables(ALUTs)DedicatedLogicRegisters(DLRs)AdaptiveLogicModules(ALMs)Fixed-to-Float16.16 f

ALTFP_CONVERT Design Example: Convert Double-Precision Floating-Point Format NumbersThis design example uses the ALTFP_CONVERT IP core to convert doub

Table 17-5: Summary of Input Values and Corresponding OutputsTime Event0 ns, start-up dataa[] value: C394 AD22 761B 9EE5hOutput value: The result[] po

ALTFP_CONVERT SignalsFigure 17-2: ALTFP_CONVERT Signalsdataa[]clockclk_eninstALTFP_CONVERTresult[]overflownanunderflowaclrTable 17-6: ALTFP_CONVERT In

Table 17-7: ALTFP_CONVERT Output SignalsPort Name Required Descriptionresult[] Yes Output for the floating-point converter. The size of this output po

ALTFP_CONVERT ParametersTable 17-8: ALTFP_CONVERT ParametersPort Name Type Required DescriptionWIDTH_EXP_INPUTInteger Yes Specifies the precision of t

Port Name Type Required DescriptionWIDTH_DATA Integer Yes Specifies the input data width.If the operation is INT2FLOAT, the WIDTH_DATA is alsoWIDTH_IN

Port Name Type Required DescriptionOPERATION Integer Yes Specifies the operating mode. Values are INT2FLOAT,FLOAT2INT, FLOAT2FLOAT, FLOAT2FIXED, andFI

ALTERA_FP_FUNCTIONS IP Core182014.12.19UG-01058SubscribeSend FeedbackALTERA_FP_FUNCTIONS FeaturesThe ALTERA_FP_FUNCTIONS IP core offers the following

Function DescriptionComparisonsMinMaxLess than (or equal)Greater than (or equal)(Not) EqualExp/Log/PowPowerExponential (Base 2, 10, e)Log (Base 2, 10,

File Name Description<my_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file thatcontains local generic and port definitions that

1. In the ALTERA_FP_FUNCTIONS parameter editor, click the Basic tab.2. Under the Performance category, in the Goal option, select Combined.3. In the T

Family Function Precision Latency fMAXALMs M10KM20KDSPBlocksLogic RegistersPrimary SecondaryArria V(5AGXFB3H4F40C5)Exp base 2Single 7 236.41 345 0 — 2

Family Function Precision Latency fMAXALMs M10KM20KDSPBlocksLogic RegistersPrimary SecondaryCyclone V(5CGXFC7D6F31C7)AbsSingle 0 -- 33 0 -- 0 0 0Doubl

Family Function Precision Latency fMAXALMs M10KM20KDSPBlocksLogic RegistersPrimary SecondaryCyclone V(5CGXFC7D6F31C7)Log base eSingle 22 181.42 482 4

Family Function Precision Latency fMAXALMs M10KM20KDSPBlocksLogic RegistersPrimary SecondaryStratix V(5SGXEA7K2F40C2)Exp base 2Single 5 387.3 351 -- 0

Family Function Precision Latency fMAXALMs M10KM20KDSPBlocksLogic RegistersPrimary SecondaryArria 10(10AX115H4F34I3SP)AbsSingle 0 -- 33 -- 0 0 0 0Doub

Family Function Precision Latency fMAXALMs M10KM20KDSPBlocksLogic RegistersPrimary SecondaryArria 10(10AX115H4F34I3SP)Log base 2Single 14 275.79 316 -

Table 18-3: TrigonometryFamily Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryArria V(5AGXFB3H4F40C5)Arc

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryArria V(5AGXFB3H4F40C5)Arctan2Single 0 43 230.2 1,

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryCyclone V(5CGXFC7D6F31C7)ArccosSingle 0 42 217.2 8

File Name Description<my_ip>.svdAllows HPS System Debug tools to view the register maps ofperipherals connected to HPS within a Qsys system.Duri

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryCyclone V(5CGXFC7D6F31C7)Arctan2Single 0 51 206.14

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryStratix V(5SGXEA7K2F40C2)ArccosSingle 0 23 291.467

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryStratix V(5SGXEA7K2F40C2)CosSingle 0 17 267.02711

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryArria 10(10AX115H4F34I3SP)ArccosSingle 0 28 270.42

Family Function PrecisionScaleBy PiLatencyfMAXALMsM10K M20KDSPBlocksLogic RegistersPrimary SecondaryArria 10(10AX115H4F34I3SP)CosSingle 0 21 336.93786

Table 18-4: FPFXPFamilyInputPrecisionOutputWidthOutputFractionLatencyfMAXALMs M10K M20KDSPBlocksLogic RegistersPrimarySecondaryArria V(5AGXFB3H4F40C5)

FamilyInputPrecisionOutputWidthOutputFractionLatencyfMAXALMs M10K M20KDSPBlocksLogic RegistersPrimarySecondaryStratix V(5SGXEA7K2F40C2)Single32 0 0 71

Table 18-5: FXPFPFamilyInputWidthInputFractionOutputPrecisionLatencyfMAXALMs M10K M20KDSPBlocksLogic RegistersPrimarySecondaryArria V(5AGXFB3H4F40C5)3

FamilyInputWidthInputFractionOutputPrecisionLatencyfMAXALMs M10K M20KDSPBlocksLogic RegistersPrimarySecondaryCycloneV(5CGXFC7D6F31C7)32 0 Single 8 230

FamilyInputWidthInputFractionOutputPrecisionLatencyfMAXALMs M10K M20KDSPBlocksLogic RegistersPrimarySecondaryStratixV(5SGXEA7K2F40C2)32 0 Single 3 579

Figure 1-6: Legacy Parameter EditorsLegacy parameter editors1. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP c

FamilyInputWidthInputFractionOutputPrecisionLatencyfMAXALMs M10K M20KDSPBlocksLogic RegistersPrimarySecondaryArria 10(10AX115H4F34I3SP)32 0 Single 3 4

ALTERA_FP_FUNCTIONS SignalsFigure 18-1: ALTERA_FP_FUNCTIONS Signalsclkb (1), (2)ALTERA_FP_FUNCTIONS q (1)a (1)areset1) The floating point an

ALTERA_FP_FUNCTIONS ParametersThese tables list the ALTERA_FP_FUNCTIONS parameters.Table 18-8: ALTERA_FP_FUNCTIONS Parameters: Functionality TabCatego

Category Parameter Values DescriptionsFunction Name• WidthConversions• Min• Max• Less than (orequal)• Greater than (orequal)• (Not) Equal• Power• Expo

Category Parameter Values DescriptionsFixed Point DataWidth 16 to 128 The bit width of the fixedpoint data port. Thisparameter is only availablewhen t

Table 18-9: ALTERA_FP_FUNCTIONS Parameters: Performance TabCategory Parameter Values DescriptionsTargetGoal• Frequency• Latency• CombinedIf the Goal i

Document Revision HistoryA2014.12.19UG-01058SubscribeSend FeedbackDocument Revision HistoryThis table lists the document revision history for the Floa

Date DocumentVersionChanges MadeJuly 2010 3.0• Updated architecture information for the followingsections:ALTFP_MATRIX_MULTALTFP_MATRIX_INV.• Added sp

The upgrade process renames and preserves the existing variation file (.v, .sv, or .vhd) as <my_variant>_BAK.v, .sv, .vhd in the project directo

Figure 1-7: Upgrading IP CoresDisplays upgrade status for all IP coresin the ProjectUpgrades all IP core that support “Auto Upgrade”Upgrades individua

Related InformationAltera IP Release NotesMigrating IP Cores to a Different DeviceIP migration allows you to target the latest device families with IP

• Support for floating-point formats.• Input support for not-a-number (NaN), infinity, zero, and normal numbers.• Optional asynchronous input ports in

ContentsAbout Floating-Point IP Cores...1-1List of Floating-Point IP Cores...

Figure 1-9: Single-Precision RepresentationThis figure shows a single-precision representation.S E M31 30 23 22 0Double-Precision FormatThe double-pre

Meaning Sign Field Exponent Field Mantissa FieldNegative Denormalized 1 All 0’s Non-zeroPositive Infinity 0 All 1’s All 0’sNegative Infinity 1 All 1’s

Figure 1-12: Fixed-Point FormatSign bitInteger bits31 0Fraction bitsFloating-Points IP Cores Output LatencyThe IP cores measure the output latency in

Floating-Point IP Cores Design FilesALTFP_INV_SQRT• altfp_inv_sqrt_DesignExample.zip (Quartus II design files)• altfp_inv_sqrt_ex_msim.zip (ModelSim-A

• ALTFP_COMPARE Design Example: Comparison of Single-Precision Format Numbers on page16-2• ALTFP_CONVERT Design Example: Convert Double-Precision Floa

ALTERA_FP_MATRIX_INV IP Core22014.12.19UG-01058SubscribeSend FeedbackALTERA_FP_MATRIX_INV FeaturesThe ALTERA_FP_MATRIX_INV IP core offers the followin

Table 2-1: ALTERA_FP_MATRIX_INV Resource Utilization and Performance for the Stratix IV Device FamilyPrecisionMatrixSizeBlocksLogic usageLatencyThroug

= (LT)-1 × L-1 = (L-1)T × L-1where a Cholesky decomposition function is needed to obtain L, a triangular matrix inversion is needed toobt

Figure 2-2: Cholesky Decomposition Function Top-level DiagramAlthough the Cholesky decomposition algorithm only operates on the lower triangular matri

Triangular Matrix InversionThe triangular matrix, L, obtained from the Cholesky decomposition function is computed using thetriangular matrix inversio

ALTERA_FP_MATRIX_MULT Signals... 3-4ALTERA_FP_MATRIX_MU

Figure 2-3: Matrix Inversion Timing DiagramsysclkenableresetloaddataindataoutoutvalidbusydoneLoading Stage Processing Stage Output StageThe following

ALTERA_FP_MATRIX_INV Design Example: Understanding the Simulation ResultsThe simulation waveform in this design example is not shown in its entirety.

Time Event12527.5 –12922.5 nsOutput stage:• The outvalid signal asserts in intervals of 8 clock cycles. These seriesof assertions signify the availabi

Matrix DataPC-based OutputMatrix42148e03 42f5794f 421b33f4 430e0587 41ff0d66 c2f579a3 c2df1c28 c2f945bc42f5794f 43d60be5 430944db 43f2dd63 42da2dd0 c3

ALTERA_FP_MATRIX_INV SignalsFigure 2-5: ALTERA_FP_MATRIX_INV SignalsdatainsysclkresetinstALTERA_FP_MATRIX_INVdataout[]busyoutvaliddoneloadenableTable

Port Name Required Descriptiondone Yes When asserted, the last output has been written. A new matrixmultiply can be started with calculate. done will

ALTERA_FP_MATRIX_MULT IP Core32014.12.19UG-01058SubscribeSend FeedbackALTERA_FP_MATRIX_MULT FeaturesThe ALTERA_FP_MATRIX_MULT IP core offers the follo

Table 3-1: ALTERA_FP_MATRIX_MULT Resource Utilization and Performance for the Arria 10 and Stratix VDevicesFamily DataFormatMatrix ASizeMatrix BSizeVe

Figure 3-2: Matrix Serialization FormatAn input matrix with M rows and N columns must be input as shown in this figure, where the Row 0 andColumn 0 el

The following lists the key features of the architecture:• Matrix A and B storage are double buffered to allow processing to happen in parallel with d

ALTFP_SQRT Design Example: Square Root of Single-Precision Format Numbers...8-3ALTFP_SQRT Design Example: Understanding the Simul

Port Name Required Descriptionreset_n No Asynchronous active low reset port.a_data Yes Matrix A input data.a_valid Yes Matrix A Avalon streaming valid

Parameter Value DescriptionVector Size Allowed values are 8,16,32, 64, 96, and 128.The size of the dot product which canbe computed in parallel. Where

ALTERA_FP_ACC_CUSTOM IP Core42014.12.19UG-01058SubscribeSend FeedbackALTERA_FP_ACC_CUSTOM FeaturesThe ALTERA_FP_ACC_CUSTOM IP core offers the followin

Table 4-1: ALTERA_FP_ACC_CUSTOM Resource Utilization and PerformanceThis table lists the resource utilization and performance information for the ALTE

Related InformationFitter Resources ReportsProvides information about Quartus II resource utilizationALTERA_FP_ACC_CUSTOM SignalsFigure 4-1: ALTERA_FP

Port Name Required Descriptionxo Yes The overflow flag for port x. The signal goes high when the exponent ofthe input x is larger than maxMSBX. The si

Category Parameter Values DescriptionAccumulator SizeMSBA — The weight of the MSB of the accumulator. Forexample, in a financial simulation, if the va

Category Parameter Values DescriptionReport — — Reports the latency of the device, which is thenumber of cycles it takes for an accumulation topropaga

ALTFP_ADD_SUB IP Core52014.12.19UG-01058SubscribeSend FeedbackALTFP_ADD_SUB FeaturesThe ALTFP_ADD_SUB IP core offers the following features:• Dynamica

DATAA[] DATAB[] SIGN BIT RESULT[] Overflow Underflow Zero NaNNormal NaN X NaN 0 0 0 1Denormal Normal 0/1 Normal 0 0 0 0Denormal Denormal 0/1 Normal 0

ALTFP_ATAN IP Core... 13-1Output Latency...

Table 5-2: ALTFP_ADD_SUB Resource Utilization and Performance for the Stratix Series of DevicesDevice Family Precision Optimiza‐tionOutputlatencyAdapt

This design example implements a floating-point adder for the addition of double-precision formatnumbers. All the optional input ports (clk_en and acl

Figure 5-2: ALTFP_ADD_SUBdataa[]datab[]add_subclockclk_eninstALTFP_ADD_SUBresult[]overflownanunderflowzeroaclrTable 5-4: ALTFP_ADD_SUB Input PortsPort

Port Name Required Descriptionoverflow Yes Overflow exception port. Asserted when the result of the addition orsubtraction, after rounding, exceeds or

Parameter Name Type Required DescriptionWIDTH_EXP Integer No Specifies the precision of the exponent. The bias ofthe exponent is always set to 2 (WIDT

ALTFP_DIV IP Core62014.12.19UG-01058SubscribeSend FeedbackALTFP_DIV FeaturesThe ALTFP_DIV IP core offers the following features:• Division functions.•

Precision Mantissa Width Latency (in clock cycles)Single Extended31 – 32 8, 18, 4133 – 34 8, 18, 4335 – 36 8, 18, 4537 – 38 8, 18, 4739 – 40 8, 18, 49

DATAA[] DATAB[] SIGN BIT RESULT[] Overflow UnderflowZero Division-by-zeroNaNDenormal NaN X NaN 0 0 0 0 1Zero Normal 0/1 Zero 0 0 1 0 0Zero Denormal0/1

Device family PrecisionOptimiza‐tionOutputlatencyLogic UsagefMAX(MHz)AdaptiveLook-UpTables(ALUTs)Dedicated LogicRegisters(DLRs)AdaptiveLogicModules(AL

Table 6-4: Summary of Input Values and Corresponding Outputs This table lists the inputs and corresponding outputs obtained from the simulation in the

ALTERA_FP_FUNCTIONS IP Core...18-1ALTERA_FP_FUNCTIONS Features...

ALTFP_DIV SignalsFigure 6-2: ALTFP_DIV Signalsdataa[]datab[]clk_enclockinstALTFP_DIVresult[]overflowunderflowzeronandivision_by_zeroaclrTable 6-5: ALT

Port Name Required Descriptionoverflow No Overflow port for the divider. Asserted when the result of the division(after rounding) exceeds or reaches i

Parameter Name Type Required DescriptionOPTIMIZE String No Specifies whether to optimize for area or for speed.Values are AREA and SPEED. A value of A

ALTFP_MULT IP Core72014.12.19UG-01058SubscribeSend FeedbackALTFP_MULT IP Core FeaturesThe ALTFP_MULT IP core offers the following features:• Multiplic

DATAA[] DATAB[] RESULT[] Overflow Underflow Zero NaNNormal Normal Zero 0 1 1 0Normal Denormal Zero 0 0 1 0Normal Zero Zero 0 0 1 0Normal Infinity Infi

Table 7-3: ALTFP_MULT Resource Utilization and Performance for Stratix IV Devices with DedicatedMultiplier CircuitryDevice Family PrecisionOutputlaten

This design example implements a floating-point multiplier for the multiplication of double-precisionformat numbers. All the optional input ports (clk

Table 7-5: ALTFP_MULT Megafunction ParametersParameter Name Type Required DescriptionWIDTH_EXP Integer No Specifies the value of the exponent. If this

Port Name Required Descriptionaclr No Synchronous clear. Source is asynchronously reset when assertedhigh.dataa[] Yes Floating-point input data input

ALTFP_SQRT82014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_SQRT IP core according to you

About Floating-Point IP Cores12014.12.19UG-01058SubscribeSend FeedbackThe Altera® floating-point megafunction IP cores enable you to perform floating-

Precision Mantissa Width Latency (in clock cycles)Single-extended3120, 3632 20, 3733 21, 3834 21, 3935 22, 4036 22, 4137 23, 4238 23, 4339 24, 4440 24

ALTFP_SQRT Resource Utilization and PerformanceThis table lists the resource utilization and performance information for the ALTFP_SQRT IP core. Thein

Figure 8-2: ALTFP_SQRT ModelSim Simulation Waveform (Output Data)This design example implements a floating-point square root function for single-preci

Figure 8-3: ALTFP_SQRT Signalsdata[]clockclk_eninstALTFP_SQRTresult[]overflownanzeroaclrTable 8-4: ALTFP_SQRT IP Core Input SignalsPort Name Required

ALTFP_SQRT ParametersTable 8-6: ALTFP_SQRT ParametersParameter Name Type Required DescriptionWIDTH_EXP Integer Yes Specifies the precision of the expo

ALTFP_EXP IP Core92014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_EXP IP core according

DATAA[] Calculation RESULT[] NaN Overflow Underflow ZeroNormal (numbersof small magnitude)edata 1 0 0 1 0Normal (negativenumbers of largemagnitude)eda

ALTFP_EXP Design Example: Understanding the Simulation ResultsThe simulation waveform in this design example is not shown in its entirety. Run the des

Time Event82.5 ns Output value: 3F80 0000hAs the input value of 1A03568Ch is a very small number, it is seen as a value that isapproaching zero, and t

Figure 9-3: ALTFP_EXP Signalsdata[]clk_enclockinstALTFP_EXPresult[]underflowzeronanunderflowaclrTable 9-4: ALTFP_EXP IP Core Input SignalsPort Name Re

IP Core Name Function OverviewALTERA_FP_ACC_CUSTOM An Application Specific AccumulatorALTERA_FP_FUNCTIONS A Collection of Floating-Point FunctionsComp

Port Name Required Descriptionnan No NaN exception output. Asserted when an invalid operation occurs.Any operation involving NaN also asserts the nan

ALTFP_INV IP Core102014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_INV IP core according

DATA[] SIGN BIT RESULT[] Underflow Zero Division_by_zeroNaNNormal 0/1 Denormal 1 1 0 0Normal 0/1 Infinity 0 0 0 0Normal 0/1 Zero 1 1 0 0Denormal 0/1

ALTFP_INV Design Example: Understanding the Simulation ResultsThe simulation waveform in this design example is not shown in its entirety. Run the des

Time Event10 ns data[] value: 7F80 0000hThis is an infinity value.107.5 ns Output value: 0000 0000hException handling ports: zero assertsThe inverse o

Table 10-5: ALTFP_INV Megafunction Output PortsPort Name Required Descriptionresult[] Yes The floating-point inverse result of the value at thedata[]i

Parameter Name Type Required DescriptionWIDTH_MAN Integer Yes Specifies the value of the mantissa. If this parameteris not specified, the default is 2

ALTFP_INV_SQRT IP Core112014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_INV_SQRT IP core

Table 11-2: Truth Table for Inverse Square Root OperationsDATA[] SIGN BIT RESULT[] Zero Division_by_zeroNaNNormal 0 Normal 0 0 0Normal 1 NaN 0 0 1Deno

ALTFP_INV_SQRT Design Example: Understanding the Simulation ResultsThe simulation waveform in this design example is not shown in its entirety. Run th

IP Catalog and Parameter EditorThe Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize andintegrate IP cores

Time Event137.5 ns Output value: FFC0 0000hException handling ports: nan assertsThe inverse square root of a negative value produces a NaN.20 ns data[

Table 11-5: ALTFP_INV_SQRT IP Core Input SignalsPort Name Required Descriptionaclr No Asynchronous clear. When the aclr port is asserted high, thefunc

Table 11-7: ALTFP_INV_SQRT Megafunction ParametersParameter Name Type Required DescriptionWIDTH_EXP Integer Yes Specifies the precision of the exponen

ALTFP_LOG122014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_LOG IP core according to your

Table 12-2: Truth Table for Natural Logarithm OperationsDATA[] SIGN BIT RESULT[] Zero NaNNormal 0 Normal 0 0Normal 1 NaN (6)0 11 (7)0 Zero 1 0Denormal

Related Information• Floating-Point IP Cores Design Example Files on page 1-16• Floating-Point IP Cores Design ExamplesProvides the design example fil

Time Event102.5 ns Output value: FF80 0000hThe natural logarithm of zero is negative infinity.5 ns data[] value: 8000 0000hThis is a negative number.1

Figure 12-3: ALTFP_LOG Signalsdata[]clk_enclockinstALTFP_LOGresult[]zeronanaclrTable 12-5: ALTFP_LOG IP Core Input SignalsPort Name Required Descripti

Port Name Required Descriptionzero No Zero exception output. Asserted when the exponent and mantissaof the output port are zero. This occurs when the

ALTFP_ATAN IP Core132014.12.19UG-01058SubscribeSend FeedbackYou can use the ports and parameters available to customize the ALTFP_ATAN megafunction ac