Altera Floating-Point Uživatelský manuál stáhnout pdf (Strana 60)

ALTFP_DIV Signals

Figure 6-2: ALTFP_DIV Signals

dataa[]

datab[]

clk_en

clock

inst

ALTFP_DIV

result[]

overflow

underflow

zero

nan

division_by_zero

aclr

Table 6-5: ALTFP_DIV Input Signals

Port Name Required Description

aclr No Asynchronous clear input for the floating-point divider. The source is

asynchronously reset when the aclr signal is asserted high.

clock Yes Clock input to the IP core.

clk_en No Clock enable to the floating-point divider. This port enables division.

This signal is active high. When this signal is low, no division takes

place and the outputs remain the same.

dataa[] Yes Numerator data input. The MSB is the sign bit, the next MSBs are the

exponent, and the LSBs are the mantissa. The size of this port is the

total width of the sign bit, exponent bits and mantissa bits.

datab[] Yes Denominator data input.The MSB is the sign bit, the next MSBs are

the exponent, and the LSBs are the mantissa. The size of this port is

the total width of the sign bit, exponent bits and mantissa bits.

Table 6-6: ALTFP_DIV Output Signals

Port Name Required Description

result[] Yes Divider output port. The division result (after rounding). As with the

input values, the MSB is the sign, the next MSBs are the exponent,

and the LSBs are the mantissa. The size of this port is the total width

of the sign bit, exponent bits, and mantissa bits.

6-6

ALTFP_DIV Signals

UG-01058

2014.12.19

Altera Corporation

ALTFP_DIV IP Core

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Altera Floating-Point Uživatelský manuál Strana 60