Altera Floating-Point Uživatelský manuál Strana 27
- Strana / 157
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
= (LT)-1 × L-1
= (L-1)T × L-1
where a Cholesky decomposition function is needed to obtain L, a triangular matrix inversion is needed to
obtain L-1, and a matrix multiplication is needed for (L-1)T × L-1.
Figure 2-1: Matrix Inversion Flow Diagram
A
A L
L
-1
L
A(L )
Matrix A
Storage 1 Storage 2
Cholesky
Decomposition
Triangular Matrix
Inversion
Matrix
Multiplication
-f
X
=
T -1
L
-1
Cholesky Decomposition Function
The functions consists of two memory and two processing blocks. One of the memory blocks is the input
matrix memory block and is loaded with the input matrix in a row order, one element at a time. However,
during processing, this block is read in a column order, one element at a time when required.
The other memory block is the processing matrix block which consists of multiple column memories to
enable an entire row to be read at once. During the loading of the input memory, the FPC datapath
preprocesses the input elements to generate the first column of the resulting triangular matrix. The top
element of the first column, l00, is the square root of the input matrix value a00. The rest of the first
column, li0 is the input value ai0 divided by l00. This preprocessing step introduces latency into the
load, during which the INIT_BUSY signal is asserted. The CALCULATE signal initiates and starts processing
after the INIT_BUSY signal is deasserted.
This figure shows the top-level architecture of the Cholesky decomposition function, where the
monolithic input memory and the column-wise processing memory, also known as the vector matrix, are
shown. The gray block is the FPC datapath section.
UG-01058
2014.12.19
Cholesky Decomposition Function
2-3
ALTERA_FP_MATRIX_INV IP Core
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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